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The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a gm/ID based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.

In this paper a simple planar quad spiral microstrip resonator is proposed with high Q, compact size and ease of fabrication. First, its structure consists of quarter wavelength resonator coupled to quad spiral resonators to improve its Q factor. Second, its equivalent circuit is presented. Third, a parametric analysis is deduced to obtain design guidelines for this novel structure. Fourth, two optimized high Q X-band and Ku-band resonators are introduced; one for high resolution microstrip fabrication facility with ultra-high loaded Q reaches 1200 and the other matches the low resolution facilities with high loaded Q of about 400. Finally, the proposed resonator is verified using fabrication and measurements. Measurements are compared to the 3D EM simulations and to the results of other published work. They are found very promising compared to single and dual spirals; above 50% enhancement in loaded Q. This proves the proposed idea and shows the technical penifits compared to the state of the art. Therefore, it could be utilized in modern microwave filters, miniaturized sensors and low phase noise oscillators.

This paper proposes an automated control system which is necessary for Lab-on-chip (LOC) applications. The control system consists of two subsystems. The first subsystem is the signal generator which is required to generate four out-of-phase signals with phases 0°, 90°, 180° and 270°. The signal generator is based on two Analog Devices AD9851 Direct Digital Synthesizers (DDS). The second subsystem of the system is the data acquisition system which is needed to acquire the output signals from the LOC. The data acquisition subsystem is implemented using Saleae Logic Pro 8. The signal generator provides a bandwidth of 5 MHz with four perfectly synced sinusoidal signals. The data acquisition also provides the same bandwidth with sampling rate of 50 MS/s. The control interface for the complete signal is implemented using National Instruments LabVIEW software which automates the whole system and facilitate further processing on the output signals.

This paper presents a low power instrumentation amplifier (IA) for the use in Internet of Things (IoT). A modified topology based on the INA321 by Texas Instruments of the two-opamp IA is used for its higher CMRR. The main design constraints are low power consumption and low noise. Two stage topology opamp is used for its capability of operating from a low supply voltage. Self-cascode technique enhances the open loop gain and allows the use of indirect compensation reducing the capacitor size. The drawback is reduced bandwidth however not a concern as many IoT applications exhibit narrow bandwidth. Post layout simulation is performed using Cadence Virtuoso 6.1.5 and TSMC 65 nm node. The designed opamp consumes 28.8 nW from a 0.4 V supply. Exhibits an open loop gain of 52 dB with phase margin 90 degrees. The IA has a fixed gain of 24 dB and bandwidth of 11 kHz. Common mode rejection of 83 dB is achieved. Total power dissipation is 89 nW.

Dielectrophoresis (DEP) is the phenomenon where a force is exerted on a particle when a non-uniform electric field is applied. It's commonly used in separating cancer cells from healthy cells or separating different strains of bacteria. DEP requires 2 perfectly out of phase signals with matched amplitude for controlling the electrical field. This paper presents a low power balanced signal generator based on the operational floating current conveyor (OFCC) for the use in lab-on-chips that use DEP levitation. The OFCC is a versatile analog current mode building block. The circuit is designed using standard TSMC 90 nm CMOS technology. The circuit consumes 11 μW from a 0.4 V single supply. The total chip area is 0.053 mm2. The generator outputs 2 signals with 0.03 dB difference in amplitude and 5 degrees in phase at 1 MHz. Post layout simulation show that the circuit provides a promising solution for Lab-on-Chip using DEP levitation techniques.

This paper describes the design of a low power current mode instrumentation amplifier dedicated to biomedical applications based on current conveyor. All MOSFETs operate in the subthreshold region yielding high energy efficiency using a single ended 0.4V supply. It's designed using standard CMOS technology which can be easily integrated into VLSI circuits. The design procedure is explained and verified by post layout results presented using TSMC 90 nm technology. Chopping technique is applied to reduce flicker noise to 3.59 μVrms for bandwidth 0.2–150 Hz. A high common mode rejection ratio of 107 dB is achieved while consuming 5.5 μW with maximum gain 41 dB. The chip area is 0.023 mm2. The obtained results demonstrate that well designed current mode circuits in subthreshold are an attractive solution for portable biomedical applications.

This paper presents a new low power Current Conveyor II (CCII). The proposed circuit uses a 0.4 V single-ended supply. The advantages of the proposed current mode readout circuit are threefold. Firstly, the proposed circuit provides extremely low power consumption while operating all MOSFETs in the subthreshold region providing the highest energy efficiency. Secondly, Self cascode technique is used to increase the gain of the differential amplifier to 65 dB. Finally, it is based on standard CMOS technology which can be easily used in VLSI circuits. Near perfect voltage/current tracking up to 1.25 / 0.8 MHz was achieved while consuming 1.7 μW.

A novel matching network and design methodology for the matching network of an inductively degenerated CMOS common source LNA at 60 GHz is presented in this paper. The design methodology minimizes the noise figure while guaranteeing the matching conditions. The new methodology depends on a developed theory in which the single ended LNA is divided into two identical parallel half sections, and the final output is the sum of these two section. The matching network is then viewed as a phase shifter with an optimum phase to cancel the noise of the other section. The design methodology is used to design an LNA using the 0.13µm CMOS technology. Simulations show a conversion gain (S21) of 28 dB, matching coefficient (S11) of −21.66 dB, minimum noise figure of 4.1 dB, and an IIP3 of −3.4 dBm. To our knowledge, the obtained NF is the best reported when compared to similar designs using the 0.13 µm technology node. The LNA consumes 12 mA from 2V supply.

A low power linearized 8-bit VCO-based ADC is presented. The proposed ADC employs a differential VCO coupling technique to enhance the VCO time resolution and a linearization switched capacitor feedback loop for improving the SNDR and VCO linearity. The loop added the programmability property to the ADC performance. The 200MSample/sec ADC was implemented in 130nm CMOS process showing an SNR/SNDR ranging from 91.4/88.3dB to 54.3/41.2dB for an input bandwidth of 500kHz–100MHz while consuming a total of 6.78mW from a 1.2V supply. The process insensitive linearization loop improves the VCO linearity from 2% to 0.17%.

A low power linearized 9-bit VCO-based ADC is presented. The proposed ADC employs a differential VCO coupling technique to enhance the VCO time resolution and a linearization switched capacitor feedback loop for improving the SNDR of the ADC. The proposed 200MHz ADC implemented in 130nm CMOS process showed an SNR/SNDR ranging from 91.4/88.3dB to 54.3/41.2dB for an input bandwidth of 500kHz - 100MHz while consuming a total of 8.3mW from a 1.2V supply.

A high speed generic Floating Point Unit (FPU) consisting of a multiplier and adder/subtractor units is proposed. A novel multiplication algorithm is proposed and used in the multiplier implementation. The new algorithm depends on dividing the multiplication operation into several smaller multiplications performed in parallel. The output from these multiplications is then manipulated in a manner to give the final result of the original multiplication operation. The adder/subtractor unit is implemented using the Leading One Detector (LOD) algorithm. In order to achieve high maximum, speed, both units were deeply pipelined. The design is written using VHDL code and mapped to Virtex2, Virtex4 and Virtex5 FPGAs. Both units can operate at more than 400 MHz on Virtex4.

This paper applies an average modeling technique to different types of switched-capacitor DC-DC converters, taking into account the circuit non-ideal parameters. An extensive set of experiments were carried out to test the validity of each model. The results show acceptable accuracy and simulation speed gain of several thousand times. This speed gain is achieved due to relaxation of the simulation timestep as opposed to traditional modeling and simulation techniques, where the simulator timestep is bound by the switching frequency. This modeling approach is most suitable for system level simulations where accuracy can be traded-off for speed.