Search

Purpose: The purpose of this study is to find a new design that can increase the sensitivity of the sensor without sacrificing the linearity. A novel and very efficient method for increasing the sensitivity of MEMS pressure sensor has been proposed for the first time. Rather than perforation, we propose patterned thinning of the diaphragm so that specific regions on it are thinner. This method allows the diaphragm to deflect more in response with regard to the pressure. The best excavation depth has been calculated and a pressure sensor with an optimal pattern for thinned regions has been designed. Compared to the perforated diaphragm with the same pattern, larger output voltage is achieved for the proposed sensor. Unlike the perforations that have to be near the edges of the diaphragm, it is possible for the thin regions to be placed around the center of the diaphragm. This significantly increases the sensitivity of the sensor. In our designation, we have reached a 60 per cent thinning (of the diaphragm area) while perforations larger than 40 per cent degrade the operation of the sensor. The proposed method is applicable to other MEMS sensors and actuators and improves their ultimate performance. Design/methodology/approach: Instead of perforating the diaphragm, we propose a patterned thinning scheme which improves the sensor performance. Findings: By using thinned regions on the diaphragm rather than perforations, the sensitivity of the sensor was improved. The simulation results show that the proposed design provides larger membrane deflections and higher output voltages compared to the pressure sensors with a normal or perforated diaphragm. Originality/value: The proposed MEMS piezoelectric pressure sensor for the first time takes advantage of thinned diaphragm with optimum pattern of thinned regions, larger outputs and larger sensitivity compared with the simple or perforated diaphragm pressure sensors. [ABSTRACT FROM AUTHOR]

Considering the trend of scaling down conventional technologies toward next-generation devices and the importance of new practical and efficient procedures in increasing the efficiency of digital computing circuits, this paper presents three full adder circuits. Suggested circuits, named Design-1 to Design-3, are proposed based on FinFET technology with channel length of 11 nm. In order to optimize energy consumption and area occupation, they have been implemented based on approximate computing with 4, 10, and 12 transistors, respectively. The main characteristics of the presented circuits lie in their utilization of the gate diffusion input technique, which has resulted in the generation of only three errors in their output. Diverse objectives for error generation have been incorporated into these circuits, positioning them as highly accurate competitors when compared to the most state-of-the-art designs. Also, due to the use of low number of transistors, which has led to low internal nodes, these circuits are in a favorable position in terms of power consumption and speed. To evaluate these circuits, extensive simulations are conducted considering various implementations, including single-bit configurations and integration within 4-bit ripple carry adders with 2 and 4 approximate bits. Based on the figure of merits used consist of diverse design parameters, Design-1 with the least number of transistors has a difference of about 85% improvement compared to the nearest competitor, while design-2 and design-3 circuits are also placed in desirable rankings. [ABSTRACT FROM AUTHOR]

The article presents two multipliers equipped with error compensation techniques, utilizing approximate 4:2 compressors to minimize energy consumption. Compared to previous approximate multipliers with error compensation circuit, the proposed designs named, "M00" and "M01", strike a good balance between accuracy and energy consumption. Although the reduction in the number of transistors has significantly decreased the energy consumption of M00, the accuracy of this design is still more than adequate for real-world applications such as image processing and neural networks. On the other hand, M01 attains high precision while consuming less energy than other multipliers. This article compares the proposed designs with existing multipliers using HSPICE tool in 7 nm FinFET technology. Moreover, the accuracy and quality of the proposed multipliers are evaluated using MATLAB. The results reveal that both proposed designs are very efficient in image processing. According to the results, M00 has the lowest energy consumption among the considered designs. M00 is about 7% better than its counterpart in terms of the power-delay-product parameter (5% Pdynamic and 48% Pstatic). M01 presents favorable results in the sharpening, smoothing, and Discrete Cosine Transform processes. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm 2 . [ABSTRACT FROM AUTHOR]

A high-speed and compact in-pixel light-to-time converter (LTC), with low power consumption and wide dynamic range is presented. By using the proposed LTC, a digital pixel sensor (DPS) based on a pulse-width modulation (PWM) scheme has been designed and fabricated in a standard 180-nm, single-poly, six-metal complementary metal oxide semiconductor (CMOS) technology. The prototype chip consists of a 16 × 16 pixel array with an individual pixel size of 21 × 21 μm 2 and a fill factor of 39% in the 180-nm CMOS technology. Experimental results show that the circuit operates at supply voltages down to 800 mV and achieves an overall dynamic range of more than 140 dB. The power consumption at 800 mV supply and room light intensity is approximately 2.85 nW. [ABSTRACT FROM AUTHOR]

This paper proposes a new pixel-level light-to-frequency converter (LFC) that operates at a low supply voltage, and also offers low power consumption, low area, wide dynamic range, and high sensitivity. By using the proposed LFC, a digital pixel sensor (DPS) based on a pulse-frequency-modulation (PFM) scheme has been designed and fabricated. The prototype chip, including an array of 16 × 16 DPS with pixel size of 23 × 23 μm 2 and 33.5% fill factor, was fabricated in a standard 180-nm CMOS technology. Experimental results show that the pixel operates with maintained output characteristics at supply voltages down to 1 V. The pixel sensor achieves an overall dynamic range of more than 142 dB and consumes 103 nW per pixel at a supply voltage of 1 V at room light intensity. The sensitivity of the LFC is very high at the lower end of the light intensity compared to the higher end which enables the ability to capture clear images. [ABSTRACT FROM AUTHOR]

Multipliers are one of the most commonly used parts in a system, responsible for performing computations, while significantly contributing to power consumption. In this article, by removing the least significant bits, a new architecture is presented to implement 3 multipliers (Mul-1, Mul-2 and Mul-3), in order to reduce complexity and power consumption. Compared to the previous works, Mul-1 has the most accuracy in addition to its low energy consumption, therefore, it has been able to deliver a good trade-off between accuracy and energy consumption. All proposed designs and existing multipliers have been simulated and compared in 7 nm FinFET technology using Hspice tool. Moreover, the accuracy and quality of the proposed approximate multipliers are also evaluated using MATLAB. The results show that Mul-1 and Mul-3 are very efficient in image processing applications. According to the results, Mul-1 outperforms its counterpart by 10%, 50% and 50% in PDP, NMED and MRED, respectively. Furthermore, Mul-3 has satisfactory MSSIM in DSP applications and is better than its counterpart by 23% and 16% in PDP and MRED. Meanwhile, Mul-2 improves PDP by nearly 53% compared to Mul-1 and has the lowest power consumption. [Display omitted] • To reduce power consumption, some least significant bits are set to zero. • To ensure accuracy in multipliers, compressors have been employed as exact. • The error compensation circuit is presented to enhance precision in the second stage. • The use of multipliers in real applications that have high computational volume. [ABSTRACT FROM AUTHOR]

In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to reducing power and energy consumption can show high reliability and have the least error at low voltages. This cell is completely free from the half-select issue, which is one of the important factors in increasing power and decreasing reliability, especially at low voltage levels for SRAM arrays. It is designed without the need of write-bit-line, which according to the proposed techniques reduces the power consumption and significantly improves the write margin, also the lack of this bit-line in the memory array can reduce the total power consumption. The used bit-line only performs for read operation, therefore it has least activity. Also, an 8 Kb memory array is proposed to be able to perform various operations with less complexity, simpler logic and lower power consumption by proposing several techniques on peripheral circuits. All obtained noise margins according to proposed techniques have the highest values among the compared cells. The average power and PDP of the cell are less than all the compared designs, so that the average power and presented FoM has been improved by 6.83% and 18.46% respectively as compared to the best value of other designs. [ABSTRACT FROM AUTHOR]

In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to reducing power and energy consumption can show high reliability and have the least error at low voltages. This cell is completely free from the half-select issue, which is one of the important factors in increasing power and decreasing reliability, especially at low voltage levels for SRAM arrays. It is designed without the need of write-bit-line, which according to the proposed techniques reduces the power consumption and significantly improves the write margin, also the lack of this bit-line in the memory array can reduce the total power consumption. The used bit-line only performs for read operation, therefore it has least activity. Also, an 8 Kb memory array is proposed to be able to perform various operations with less complexity, simpler logic and lower power consumption by proposing several techniques on peripheral circuits. All obtained noise margins according to proposed techniques have the highest values among the compared cells. The average power and PDP of the cell are less than all the compared designs, so that the average power and presented FoM has been improved by 6.83% and 18.46% respectively as compared to the best value of other designs. [ABSTRACT FROM AUTHOR]

In this paper, a robust 12T-SRAM memory cell at sub-threshold voltage is designed to reduce power consumption for low power applications, that in addition to reducing power consumption can perform well at high frequencies and remain stable. For the write operation, a new method has been used that removes the write bit line and uses the supply voltage in each cell for this operation and only by applying control signals. Also, the embedded bit line is used only for read operations and reduces the activity of the bit line, and due to being floating and the way of writing, eliminates the Precharge and Write Driver circuits, so, part of the power and area consumption has been reduced. According to the techniques used, the write and read noise margin is significantly improved and the write operation become easier to perform. Also due to the existence of a separate path for the read operation, RSNM is equaled to the HSNM. The average cell power at the frequency of 100 MHz for low power applications and 0.2V supply voltage, as compared to the best previous designs, has been improved by 34.9% and the leakage power of the hold state has been reduced by 27.6% and PDP has been improved by more than 35.2%, further, the maximum operating frequency of the cell has been increased by 39.1%, while it operates with the sub-threshold voltage of 0.2V to the frequency of 2.173 GHz. [ABSTRACT FROM AUTHOR]

A new design of a MEMS bionic vector hydrophone based on piezoelectric transduction has been proposed. The designed hydrophone has a higher sensitivity in comparison to its previous counterparts. Readout electronics includes embedded MOSFETs and external operational amplifiers. MOSFETs with piezoelectric gates are integrated to the beams and have been used as the strain to electrical current transducers. The drains of the MOSFETs have been connected to operational amplifiers that convert the transistor currents to the voltage and also amplify the output. The changes in the channel length and mobility are negligible and the transistor current is merely under the influence of the pressure induced charges on the piezoelectric surface which directly produce the vertical electric field. Designed hydrophone characterized with the sensitivity up to −146.2 ​dB (Ref. 1 ​V/μPa) for frequencies up to about 3 ​kHz. The results verify the possibility of utilizing the proposed design as an underwater acoustic sensor with a high sensitivity and a wide frequency range. [ABSTRACT FROM AUTHOR]