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608 results on '"Henkel, Jorg"'

1. LightFAt: Mitigating Control-flow Explosion via Lightweight PMU-based Control-flow Attestation

Author

Gonzalez-Gomez, Jeferson, Nassar, Hassan, Bauer, Lars, and Henkel, Jorg

Subjects
Computer Science - Cryptography and Security
Abstract

With the continuous evolution of computational devices, more and more applications are being executed remotely. The applications operate on a wide spectrum of devices, ranging from IoT nodes with low computational capabilities to large cloud providers with high capabilities. Remote execution often deals with sensitive data or executes proprietary software. Hence, the challenge of ensuring that the code execution will not be compromised rises. Remote Attestation deals with this challenge. It ensures the code is executed in a non-compromised environment by calculating a potentially large sequence of cryptographic hash values. Each hash calculation is computationally intensive and over a large sequence the overhead becomes extremely high. In this work, we propose LightFAt: a Lightweight Control Flow Attestation scheme. Instead of relying on the expensive cryptographic hash calculation, LightFAt leverages the readings from the processor's Performance Monitor Unit (PMU) in conjunction with a lightweight unsupervised machine learning (ML) classifier to detect whether a target application's control flow is compromised, hence improving the system's security. On the verifier's side, LightFAt reaches a detection accuracy of over 95%, with low false-negative and false-positive rates., Comment: This official version of this paper will appear in the 2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

Published
2024

2. MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs

Author

Alrahis, Lilas, Nassar, Hassan, Krautter, Jonas, Gnad, Dennis, Bauer, Lars, Henkel, Jorg, and Tahoori, Mehdi

Subjects
Computer Science - Cryptography and Security
Abstract

The security of cloud field-programmable gate arrays (FPGAs) faces challenges from untrusted users attempting fault and side-channel attacks through malicious circuit configurations. Fault injection attacks can result in denial of service, disrupting functionality or leaking secret information. This threat is further amplified in multi-tenancy scenarios. Detecting such threats before loading onto the FPGA is crucial, but existing methods face difficulty identifying sophisticated attacks. We present MaliGNNoma, a machine learning-based solution that accurately identifies malicious FPGA configurations. Serving as a netlist scanning mechanism, it can be employed by cloud service providers as an initial security layer within a necessary multi-tiered security system. By leveraging the inherent graph representation of FPGA netlists, MaliGNNoma employs a graph neural network (GNN) to learn distinctive malicious features, surpassing current approaches. To enhance transparency, MaliGNNoma utilizes a parameterized explainer for the GNN, labeling the FPGA configuration and pinpointing the sub-circuit responsible for the malicious classification. Through extensive experimentation on the ZCU102 board with a Xilinx UltraScale+ FPGA, we validate the effectiveness of MaliGNNoma in detecting malicious configurations, including sophisticated attacks, such as those based on benign modules, like cryptography accelerators. MaliGNNoma achieves a classification accuracy and precision of 98.24% and 97.88%, respectively, surpassing state-of-the-art. We compare MaliGNNoma with five state-of-the-art scanning methods, revealing that not all attack vectors detected by MaliGNNoma are recognized by existing solutions, further emphasizing its effectiveness. Additionally, we make MaliGNNoma and its associated dataset publicly available., Comment: Will appear in the 2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

Published
2024

3. Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications

Author

Henkel, Jorg, primary, Siddhu, Lokesh, additional, Bauer, Lars, additional, Teich, Jurgen, additional, Wildermann, Stefan, additional, Tahoori, Mehdi, additional, Mayahinia, Mahta, additional, Castrillon, Jeronimo, additional, Khan, Asif Ali, additional, Farzaneh, Hamid, additional, Lima, Joao Paulo C. De, additional, Chen, Jian-Jia, additional, Hakert, Christian, additional, Chen, Kuan-Hsun, additional, Yang, Chia-Lin, additional, and Cheng, Hsiang-Yun, additional

Published
2023
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4. Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-Based Accelerators.

Author

Nassar, Hassan, Bauer, Lars, and Henkel, Jorg

Abstract

Physical unclonable functions (PUFs) are a handy security primitive for resource-constrained devices. They offer an alternative to the resource-intensive classical hash algorithms. Using the IC differences resulting from the fabrication process, PUFs give device-specific outputs (responses) when given the same inputs (challenges). Hence, without using a device-specific key, PUFs can generate device-specific responses. FPGAs are one of the platforms that are heavily studied as a candidate for PUF implementation. The idea is that a PUF that is designed as an HDL code can be used as part of the static design or as a dynamic accelerator. Previous works studied PUF implementation as part of the static design. In contrast to the state-of-the-art, this letter studies PUFs when used as runtime reconfigurable accelerators. In this letter, we find that not all regions of an FPGA are equally suitable for implementing different PUF types. Regions, where clock routing resources exist, are the worst suited for PUF implementation. Moreover, we find out that for certain PUF types, the property of dynamic partial reconfiguration can lead to performance degradation if not applied carefully. When static routing passing through the region increases, the PUF performance degrades significantly. [ABSTRACT FROM AUTHOR]

Published
2023
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8. Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers

Author

Armeniakos, Giorgos, Zervakis, Georgios, Soudris, Dimitrios, Tahoori, Mehdi B., and Henkel, Jorg

Abstract

Printed electronics (PEs) promises on-demand fabrication, low nonrecurring engineering costs, and subcent fabrication costs. It also allows for high customization that would be infeasible in silicon, and bespoke architectures prevail to improve the efficiency of emerging PE machine learning (ML) applications. Nevertheless, large feature sizes in PE prohibit the realization of complex ML models in PE, even with bespoke architectures. In this work, we present an automated, cross-layer approximation framework tailored to bespoke architectures that enable complex ML models, such as multilayer perceptrons (MLPs) and support vector machines (SVMs), in PE. Our framework adopts cooperatively a hardware-driven coefficient approximation of the ML model at algorithmic level, a netlist pruning at logic level, and a voltage overscaling at the circuit level. Extensive experimental evaluation on 12 MLPs and 12 SVMs and more than 6000 approximate and exact designs demonstrates that our model-to-circuit cross-approximation delivers power and area optimal designs that, compared to the state-of-the-art exact designs, feature on average 51% and 66% area and power reduction, respectively, for less than 5% accuracy loss. Finally, we demonstrate that our framework enables 80% of the examined classifiers to be battery-powered with almost identical accuracy with the exact designs, paving thus the way toward smart complex printed applications.

Published
2023
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9. Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits

Author

Armeniakos, Giorgos, Zervakis, Georgios, Soudris, Dimitrios, Tahoori, Mehdi B., and Henkel, Jorg

Abstract

Printed Electronics (PE) exhibits on-demand, extremely low-cost hardware due to its additive manufacturing process, enabling machine learning (ML) applications for domains that feature ultra-low cost, conformity, and non-toxicity requirements that silicon-based systems cannot deliver. Nevertheless, large feature sizes in PE prohibit the realization of complex printed ML circuits. In this work, we present, for the first time, an automated printed-aware software/hardware co-design framework that exploits approximate computing principles to enable ultra-resource constrained printed multilayer perceptrons (MLPs). Our evaluation demonstrates that, compared to the state-of-the-art baseline, our circuits feature on average 6x (5.7x) lower area (power) and less than 1% accuracy loss.

Published
2023
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20. Massively Parallel Circuit Setup in GPU-SPICE

Author

van Santen, Victor M., Diep, Fu Lam Florian, Henkel, Jorg, and Amrouch, Hussam

Abstract

SPICE simulations are the industry standard to analyze circuits for decades. However, they are computationally complex as each circuit is simulated at the transistor-level where individual transistor is modeled with dozens of sophisticated equations. This limits the practicality of SPICE simulations to relatively small circuits. However, this is in a direct conflict with the ever-increasing demands of circuit designers in which SPICE simulations for large circuits (e.g., DSPs, AES, etc.) at full accuracy are inevitably required to fulfill new industrial standards like automotive safety ISO 26262 with tool confidence level 1. To accelerate SPICE simulation without sacrificing accuracy, state-of-the-art approaches have started to employ GPUs to parallelize the LU-factorization and device linearization phases. Instead of focusing on these phases, this article demonstrates for the first time that when large circuits come into play, a new and equally important performance bottleneck emerges at the circuit setup phase. Speeding up the circuit setup phase in SPICE is our key focus in this paper. Our two implementations demonstrate that our GPU-based circuit setup reduces the analysis time from 4.5 days to merely 89 seconds for a 256-bit multiplier, which consists of more than 1M transistors. Our achieved speedup is 4396x compared to the baseline (open-source NGSPICE) and more than 2x compared to commercial (HSPICE and Spectre) SPICE circuit setup.

Published
2023
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21. Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory

Author

Holscher, Nils, Hakert, Christian, Nassar, Hassan, Chen, Kuan-Hsun, Bauer, Lars, Chen, Jian-Jia, and Henkel, Jorg

Abstract

Emerging nonvolatile memory yields, alongside many advantages, technical shortcomings, such as reduced cell lifetime. Although many wear-leveling approaches exist to extend the lifetime of such memories, usually a tradeoff for the granularity of wear leveling has to be made. Due to iterative write schemes (repeatedly sense and write), wear out of memory in certain systems is directly dependent on the written bit value and thus can be highly imbalanced, requiring dedicated bit-wise wear leveling. Such a bit-wise wear leveling so far has only be proposed together with a special hardware support. However, if no dedicated hardware solutions are available, especially for commercial off-the-shelf systems with nonvolatile memories, a software solution can be crucial for the system lifetime. In this work, we propose entirely software-based bit-wise wear leveling, where the position of bits within CPU words in the main memory is rotated on a regular basis. We leverage the LLVM intermediate representation to adjust load and store operations of the application with a custom compiler pass. Experimental evaluation shows that the lifetime by applying local rotation within the CPU word can be extended by a factor of up to $21\times $ . We also show that our method can incorporate with coarser-grained wear leveling, e.g., on block granularity and assist achievement of higher lifetime improvements.

Published
2023
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