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Semiconductor device manufacturing has seen a constant decrease in transistors gate dimensions over the course of the last six decades, which also led to an increased influence of slight variations like random dopant variations and varying oxide thickness from manufacturing the physical instances. In the design of microelectronic chips, device mismatch usually degrades the performance of a system and thus is minimized as far as possible by design techniques or auxiliary systems within a chip. Physical Unclonable Functions are a promising alternative to storing secure encryption keys in non-volatile memory and utilize device mismatch as a source of unpredictable but static information contained in the physics of an integrated circuit itself. Physical Unclonable Functions have raised interest especially in the field of low-power IoT devices due to their small size, low costs, low power requirements and intrinsic resilience against physical tampering. In this thesis, techniques to enhance delay based Physical Unclonable Functions in the analog and the digital domain are investigated and analyzed. Arbiter PUFs are improved by a two-fold approach: First, custom sizing of transistors is investigated with respect to scaling effects on the ratio between mismatch and electrical noise in order to increase the reproducibility of measurement readouts. Second, a redesign of the measurement circuitry is investigated where the arbitration circuitry is extended to also function as a deadzone detector. This approach is complemented by feedback repetitive measurements, similar to oscillators, in order to avoid readouts with a minor phase difference, which would be strongly affected by electrical noise. Ring oscillators on FPGAs are investigated regarding their reproducibility and their individual bias based on their location on the chip. Counter failures occurring in high frequency oscillations are strongly reduced by a combination of an improved counter design, reference normalization and an additional feedback path of the ring oscillator for glitch avoidance. Analysis of the areal mismatch distribution is carried out to identify systematic and thus predictable bias.

In diesem Beitrag wird eine Auswahl von Methoden zur Verbesserung integrierter CMOS PUFs vorgestellt. Am Beispiel der Arbiter-PUF zeigen wir, dass sowohl die PUF-definierenden Zufallsquellen erheblich optimiert werden können, als auch die ergänzende Messschaltung. Wir zeigen, dass insbesondere die Sensitivität der Gesamtschaltung gegenüber elektrischem Rauschen stark reduziert werden kann., acceptedVersion

This paper presents a novel approach of deriving Physical Unclonable Functions (PUF) from correction circuits measuring and digitizing non-linearities of data converters. The often digitally available correction data can then be used to generate a fingerprint of the chip. The general concept is presented and then specifically evaluated on an existing Delta-Sigma (∆Σ) modulator whose outermost feedback DAC mismatches are greatly influencing the overall performance and thus need correction. The applied mixed-signal correction scheme reveals the intrinsic mismatches which are firstly used to linearize the ∆Σ modulator, but which can also be further analyzed. The intra-Hamming distance is initially determined to values less than 6% at nominal conditions and could be further reduced to less than 2% by applying different encodings. Regarding the distinctness of devices, the inter-Hamming distance is highly stable under all circumstances with a value very close to 50%. Though the influence of varying environmental conditions on the stability of repeated PUF readouts is negligible, inevitable deviations in the correction coefficients increase the intra-Hamming distance with respect to nominal conditions. As a result, 80 highly stable identification bits are obtained from the exemplarily used ∆Σ modulator., acceptedVersion

Like every integrated circuit, Arbiter-PUFs suffer from any ambience variations such as electrical noise, supply voltage variations and temperature fluctuations. In this work, we show that most bit-errors are related to small phase differences, for which noise dominates the readout bit value. We present an approach eliminating this influence by modifying the arbitration circuit part into an eye-opening oscillator. By utilizing the deadzone of two D-Flip-Flops, the decision about the response is delayed until the phase difference becomes significant enough. With this modification, we could increase the PUFs initial bit-error rate of 3.31% to almost zero. We also highlight important design choices for this solution, like the setup-time of the D-Flip-Flops and the minimum number of enforced oscillations., acceptedVersion

This paper presents a simple yet effective way of improving delay based Physical Unclonable Functions by changing transistor gate sizes only. All utilized components of an Arbiter PUF were simulated in a 90nm CMOS process with sweeps applied to each gate dimension. By evaluating an Arbiter PUF consisting of the proposed enhanced components, we show that the intra Hamming distance can be decreased by over 60% and the inter Hamming distance can be fixed at 50%., acceptedVersion