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Superconducting Digital (SCD) technology offers significant potential for enhancing the performance of next generation large scale compute workloads. By leveraging advanced lithography and a 300 mm platform, SCD devices can reduce energy consumption and boost computational power. This paper presents a cross-layer modeling approach to evaluate the system-level performance benefits of SCD architectures for Large Language Model (LLM) training and inference. Our findings, based on experimental data and Pulse Conserving Logic (PCL) design principles, demonstrate substantial performance gain in both training and inference. We are, thus, able to convincingly show that the SCD technology can address memory and interconnect limitations of present day solutions for next-generation compute systems., Comment: 8 figures

Scaling superconducting digital circuits requires fundamental changes in the current material set and fabrication process. The transition to 300 mm wafers and the implementation of advanced lithography are instrumental in facilitating mature CMOS processes, ensuring uniformity, and optimizing the yield. This study explores the properties of NbxTi(1-x)N films fabricated by magnetron DC sputtering on 300 mm Si wafers. As a promising alternative to traditional Nb in device manufacturing, NbxTi(1-x)N offers numerous advantages, including enhanced stability and scalability to smaller dimensions, in both processing and design. As a ternary material, NbxTi(1-x)N allows engineering material parameters by changing deposition conditions. The engineered properties can be used to modulate device parameters through the stack and mitigate failure modes. We report characterization of NbxTi(1-x)N films at less than 2% thickness variability, 2.4% Tc variability and 3% composition variability. The films material properties such as resistivity (140-375 {\Omega}cm) and critical temperature Tc (4.6 K - 14.1 K) are correlated with stoichiometry and morphology of the films. Our results highlight the significant influence of deposition conditions on crystallographic texture along the films and its correlation with Tc., Comment: 8 pages 8 figures

Superconducting digital Pulse-Conserving Logic (PCL) and Josephson SRAM (JSRAM) memory together enable scalable circuits with energy efficiency 100x beyond leading-node CMOS. Circuit designs support high throughput and low latency when implemented in an advanced fabrication stack with high-critical-current-density Josephson junctions of 1000$\mu$A/$\mu$m$^2$. Pulse-conserving logic produces one single-flux-quantum output for each input, and includes a three-input, three-output gate producing logical or3, majority3 and and3. Gate macros using dual-rail data encoding eliminate inversion latency and produce efficient implementations of all standard logic functions. A full adder using 70 Josephson junctions has a carry-out latency of 5ps corresponding to an effective 12 levels of logic at 30 GHz. JSRAM (Josephson SRAM) memory uses single-flux-quantum signals throughout an active array to achieve throughput at the same clock rate as the logic. The unit cell has eight Josephson junctions, signal propagation latency of 1ps, and a footprint of 2$\mu$m$^2$. Projected density of JSRAM is 4 MB/cm$^2$, and computational density of pulse-conserving logic is on par with leading node CMOS accounting for power densities and clock rates., Comment: 6 pages, 2 figures

We describe a fabrication stackup for digital logic with 16 superconducting NbTiN layers, self-shunted a-silicon barrier Josephson Junctions (JJs), and low loss, high-$\kappa$ tunable HZO capacitors. The stack enables 400 MJJ/cm$^2$ device density, efficient routing, and AC power distribution on a resonant network. The materials scale beyond 28nm lithography and are compatible with standard high-temperature CMOS processes. We report initial results for two-metal layer NbTiN wires with 50nm critical dimension. A semi-ascendance wire-and-via process module using 193i lithography and 50nm critical dimension has shown cross-section uniformity of 1%=1s across the 300mm wafer, critical temperature of 12.5K, and critical current of 0.1mA at 4.2K. We also present a new design of the resonant AC power network enabled by NbTiN wires and HZO MIM capacitors. The design matches the device density and provides a 30 GHz clock with estimated efficiency of up to 90%. Finally, magnetic imaging of patterned NbTiN ground planes shows low intrinsic defectivity and consistent trapping of vorteces in 0.5 mm holes spaced on a 20 $\mu$m x 20 $\mu$m grid., Comment: 7 pages, 3 figures

Interconnect properties position superconducting digital circuits to build large, high performance, power efficient digital systems. We report a board-to-board communication data link, which is a critical technological component that has not yet been addressed. Synchronous communication on chip and between chips mounted on a common board is enabled by the superconducting resonant clock/power network for RQL circuits. The data link is extended to board-to-board communication using isochronous communication, where there is a common frequency between boards but the relative phase is unknown. Our link uses over-sampling and configurable delay at the receiver to synchronize to the local clock phase. A single-bit isochronous data link has been demonstrated on-chip through a transmission line, and on a multi-chip module (MCM) through a superconducting tape between driver and receiver with variable phase offset. Measured results demonstrated correct functionality with a clock margin of 3 dB at 3.6 GHz, and with 5 fJ/bit at 4.2 K.

Superconducting digital circuits are a promising approach to build packaged-level integrated systems with high energy-efficiency and computational density. In such systems, performance of the data link between chips mounted on a multi-chip module (MCM) is a critical driver of performance. In this work we report a synchronous data link using Reciprocal Quantum Logic (RQL) enabled by resonant clock distribution on the chip and on the MCM carrier. The simple physical link has only four Josephson junctions and 3 fJ/bit dissipation, including a 300 W/W cooling overhead. The driver produces a signal with 35\,GHz analog bandwidth and connects to a single-ended receiver via 20 $\Omega$ Nb Passive Transmission Line (PTL). To validate this link, we have designed, fabricated and tested two 32$\times$32 mm$^2$ MCMs with eight 5$\times$5 mm$^2$ chips connected serially and powered with a meander clock, and with four 10$\times$10 mm$^2$ chips powered with a 2 GHz resonant clock. The meander clock MCM validates performance of the data link components, and achieved 5.4 dB AC bias margin with no degradation relative to individual chip test. The resonator MCM validates synchronization between chips, with a measured AC bias margin up to 4.8 dB between two chips. The resonator MCM is capable of powering circuits of 4 million Josephson junctions across the four chips with a projected 10 Gbps serial data rate., Comment: 8 pages, 8 figures

The true-differential superconductor on-chip amplifier has complementary outputs that float with respect to chip ground. This improves signal integrity and compatibility with the receiving semiconductor stage. Both source-terminated and non-source-terminated designs producing 4mV demonstrated rejection of a large common mode interference in the package. Measured margins are $\pm$8.5% on the output bias, and $\pm$28% on AC clock amplitude. Waveforms and eye diagrams are taken at 2.9-10Gb/s. Direct measurement of bit-error rates are better than the resolution limit of 1e-12 at 2.9Gb/s, and better than 1e-9 at 10Gb/s.

Interconnects are a major discriminator for superconducting digital technology, enabling energy efficient data transfer and high-bandwidth heterogeneous integration. We report a method to simulate propagation of picosecond pulses in superconducting passive transmission lines (PTLs). A frequency-domain propagator model obtained from the Ansys High Frequency Structure Simulator (HFSS) field solver is incorporated in a Cadence Spectre circuit model, so that the particular PTL geometry can be simulated in the time-domain. The Mattis-Bardeen complex conductivity of the superconductor is encoded in the HFSS field solver as a complex-conductivity insulator. Experimental and simulation results show that Nb 20 Ohm microstrip PTLs with 1um width can support propagation of a single-flux-quantum pulse up to 7mm and a double-flux-quantum pulse up to 28mm.

A circuit-simulation-based method is used to determine the thermally-induced bit error rate of superconducting logic circuits. Simulations are used to evaluate the multidimensional Gaussian integral across noise current sources attached to the active devices. The method is data-assisted and has predictive power. Measurement determines the value of a single parameter, effective noise bandwidth, for each error mechanism. The errors in the distributed networks of comparator-free RQL logic nucleate across multiple Josephson junctions, so the effective critical current is about three times that of the individual devices. The effective noise bandwidth is only 6-23% of the junction plasma frequency at a modest clock rate of 3.4GHz, which is 1% of the plasma frequency. This analysis shows the ways measured bit error rate comes out so much lower than simplistic estimates based on isolated devices.

We report the design and test of Reciprocal Quantum Logic shift-register yield vehicles consisting of up to 72,800 Josephson junction devices per die, the largest digital superconducting circuits ever reported. Multiple physical layout styles were matched to the MIT Lincoln Laboratory foundry, which supports processes with both four and eight metal layers and minimum feature size of 0.5 {\mu}m. The largest individual circuits with 40,400 junctions indicate large operating margins of $\pm$20% on AC clock amplitude. In one case the data were reproducible to the accuracy of the measurement, $\pm$1% across five thermal cycles using only the rudimentary precautions of passive mu-metal magnetic shielding and a controlled cool-down rate of 3 mK/s in the test fixture. We conclude that with proper mitigation techniques, flux-trapping is no longer a limiting consideration for very-large-scale-integration of superconductor digital logic.

Reciprocal Quantum Logic combines the speed and power-efficiency of single-flux quantum superconductor devices with design features that are similar to CMOS. We have demonstrated an 8-bit carry look-ahead adder in the technology using combinational gates with fanout of four and non-local interconnect. Measured power dissipation of the fully active circuit is only 510 nW at 6.2GHz. Latency is only 150 ps at a clock rate of 10GHz., Comment: 6 pages, 7 figures

We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses AC power carried on a transmission line, which also serves as a clock. Using simple experiments we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins and low BER. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of Single-Flux- Quantum signals with the design methodology of CMOS, including low static power dissipation, low latency combinational logic, and efficient device count., Comment: 7 pages, 5 figures