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Fractional-order calculus exhibits clear advantages over modeling the nonlinear and complex physics phenomena. In this article, fractional-order calculus is introduced to the field of on-chip inductor modeling. A novel fractional-order 1- $\pi $ inductor equivalent circuit model is proposed to characterize on-chip inductors based on silicon-benzocyclobutene (Si-BCB) technology. The proposed model, which contains six integer-order circuit elements and three fractional-order elements, is sufficient to describe frequency-dependent effects, such as the skin effect, proximity effect, and distributed effect. Three fractional-order elements (one fractional-order inductor and two fractional-order capacitors) introduced in the above model are major contributors to improving the model’s accuracy and bandwidth. The parameter extraction method is discussed in this article, and the direct simulation method is employed to solve fractional-order equations. The accuracy of the proposed fractional-order model is validated up to 40 GHz. An excellent agreement is observed between the model and the measurements.

International audience; In this work, we present an ultra-high Q cavity at Terahertz (THz) frequencies. The designed cavity is built on a low loss suspended silicon (Si) waveguide. The substrate removal under the waveguide and the use of optimized deep reactive ion etching processing is the main reason for observing very low losses of this design α< 0.09 dB/mm. This very low loss behavior of this designed platform is also demonstrated by the measurement of a 1D photonic wire crystal cavity with Q>18000. Different cavity layouts are adjusted in order to maximize the transmittance while maintaining high Q. A design with reduced number of etched crystal holes achieve a Q>1500 and high transmittance T>70%. These structures are presented at sub-mm waves (around 600GHz) for the design of a gas sensor in this frequency region, but the principles can be scaled and redesigned for other frequencies in the THz band.

We used a microwave dielectric resonator to study how the process of thermal oxidation of high resistivity silicon wafers reduces the wafer microwave resistivity. Measurements were performed before surface thermal oxidation, after the oxidation, and after wet oxide removal. We show that the process of oxide growth decreases the microwave resistivity of the wafer from approximately 20 kΩ cm to as low as 400 Ω cm (typically to 1–2 kΩ cm), depending on the dielectric layer thickness and the growth process conditions. After the wet removal of SiO2, the resistivity of the wafers increased, but it did not reach the initial value.

We demonstrate that the highly-resistive Si substrate in GaN-on-Si RF HEMTs does not act as an insulator, but instead behaves as a conductive ground plane for static operation and can cause significant back-gate induced current collapse. Substrate ramp characterization of the buffer shows good agreement with device simulations and indicates that the current collapse is caused by charge-redistribution within the GaN layer. Potential solutions which alter charge storage and leakage in the epitaxy to counter this effect are then presented.

Deep level doping compensation concept using elemental gold is utilised to create effectively high resistivity silicon substrates for the use in GHz range. Bias-dependent substrate losses associated with parasitic surface conduction is fully suppressed, indicated by the constant attenuation loss of 0.19 dB/mm at 40 GHz for the coplanar waveguides fabricated on the substrates. In addition to that, the incorporation of slow-cooling treatment in the annealing procedure proves that further increase in substrate resistivity can be achieved for Czochralski-grown silicon substrates, rising up its potential as one of the alternative substrates for radio-frequency monolithic microwave integrated circuits applications.

Radio-Frequency (RF) losses on High-Resistivity Silicon (HRS) substrates were studied for several different surface passivation layers comprising thin-films of SiC, SiN and SiO 2 In many combinations, losses from conductive surface channels were reduced and increasing the number of interfaces between thin-films was found to be beneficial. In some cases the surface losses were completely eliminated. For example, with plasma-enhanced chemical-vapor deposition (PECVD) α-SiC layers up to a few tens of nm thick and exposed to nitridation or SiN growth at 850°C to form a SiC:N interface layer, values for the total losses of 1.6 dB/cm were achieved. Analysis of these layers was performed by using temperature dependent measurements of the RF losses on Coplanar Waveguides (CPWs), the capacitance-voltage characteristics and the sheet resistance along the Si surface. The overall results can be explained by assuming that the thin-films are so defected that they allow vertical current paths to highly-resistive interface layers where both fixed and mobile charge can be stored.

This paper analyses RF substrate losses and non-linearity on Si-based substrates. Through measurements it is shown that trap-rich high resistivity silicon and porous silicon substrates are virtually lossless up to 120 °C. Although, RF losses and CPW attenuation increases with temperature on both Si-based solutions, they remain acceptable for high temperature RF applications. Porous locally grown silicon shows better linearity than a comparable trap-rich high-resistivity (HR) Si substrate up to 175°C. Both Si-based solutions are considered as promising substrates for RF integration and system-on-chip applications. © 2013 Elsevier B.V. All rights reserved.

An electrically tunable bandpass filtering balun (BPF-Balun) on engineered substrate embedded with patterned Permalloy (Py) thin film is designed and implemented for the first time. The tunability of the BPF-Balun is realized through tuning RF characteristics of the engineered substrate. Embedded with patterned Py thin film which has high and current-dependent permeability, the developed engineered substrate has electrically tunable equivalent permeability. The center frequency of BPF-Balun on engineered substrate thus becomes tunable with different DC current. Patterning of Py film is analyzed and utilized to increase its FMR up to GHz range. The proposed BPF-Balun is fabricated on Rogers 4350 substrate while the engineered substrate is developed separately with high resistivity silicon embedded with patterned Py thin film. Tunable BPF-Balun is implemented through bonding the Rogers 4350 on the top of engineered substrate. The measured results show that the center frequency of the BPF-Balun can be tuned continuously from 1.49GHz to 1.545GHz with applied DC current adjusted from 0mA to 500mA. The measured magnitude imbalance and phase difference of the two balanced outputs are within 0.5dB and 180°± 5° for the whole frequency range. Larger tunability can be achieved with patterned Py thin film with optimized thickness.

Soleniod-like transformers based on a traveling-wave design and using advanced through silicon via process technology are reported for operation at frequencies from 1 to 14 GHz. The symmetrical 1:1 transformers are designed as compact slow-wave transmission-line structures with well-defined signal return paths. One-, two-, three-, and four-turn transformers have 1-dB bandwidths ranging from 6 to 9.2 GHz, and midband insertion losses from 0.24 to 0.37 dB. The measured intrinsic loss is 0.46 dB or less up to 10 GHz, and 0.97 dB up to 14 GHz. Relatively simple and scalable physically based lumped-element circuit models accurately predict the performance of these low parasitic transformers.

In this work 3 different types of UNIBOND™ Silicon-on-Insulator (SOI) wafers including one standard and two types of trap-rich high resistivity HR-SOI substrates provided by SOITEC are studied. The DC and RF performances of these wafers are compared by means of passive and active devices, coplanar waveguide (CPW) lines and partially-depleted (PD) SOI MOSFETs, respectively.

Ce travail de thèse étudie les moyens d’étendre les zones de charge d’espace des photodiodes PN d’un imageur CMOS afin d’améliorer la collection des charges photogénérées dans le silicium, en particulier dans le proche infra-rouge. Deux possibilités sont abordées : l’augmentation de la tension de polarisation des photodiodes et la diminution du dopage du silicium. Dans un premier temps, une étude théorique articulée autour de modèles analytiques et de simulations TCAD montre les difficultés technologiques pour parvenir à une augmentation de polarisation des photodiodes, ainsi que les conséquences de l’utilisation de substrats résistifs sur les éléments de l’imageur et sur ses performances. Ces simulations permettent de définir les éléments influençant l’extension de la charge d’espace d’un pixel. Sur la base de cette étude, un imageur CMOS à pixel 3T a été développé et fabriqué sur substrat float-zone très fortement résistif afin de valider les observations théoriques. La caractérisation de ce composant confirme la dépendance de la zone dépeuplée à la conception du pixel. Elle démontre également la corrélation entre l’extension des zones dépeuplées et les performances électro-optiques. Des règles de conception sont définies permettant d’optimiser les performances tout en limitant les courants de fuite entre pixels. This work investigates solutions to extend the space charge region in CMOS image sensors in order to enhance the photo-generatedcharge collection from near-infraredradiations. Photodiode bias increase and low doped silicon substrate are proposed for this study. A theoretical analysis based on analytical model and TCAD simulations shows technological difficulties for photodiode bias in crease and the consequences of using high-resistivity silicon substrates on the imager performances. Space charge region dependency on the pixel design is assessed through simulations. A 3T pixel CMOS image sensor was developed and fabricated on a high resistivity float-zone silicon. Sensor characterization confirms space charge region dependency on the pixel design and the correlation between its extension and electro-optical performances. Design rules are defined to optimize electro-optical performances while limiting punchthrough current in the pixels array.

Chip scale terahertz dielectric waveguides, consisting out of high resistivity silicon as a core material have been fabricated. The waveguide loss is measured to be similar to 1dB/cm at both 1 THz and 2.5 THz.

In this paper, dielectric ribbon waveguides (DRWs) are designed to work at 750–1000 GHz. In this frequency band, the Deep Reactive Ion Etching (DRIE) of high resistivity silicon fabrication process is selected to fabricate the DRW. Our experiments show that the average attenuation constant of DRW is merely 0.107dB/mm at 750–1000GHz. Good agreements between the measured and simulated results are observed.

International audience; The dielectric properties of coplanar propagation waveguides (CPW) designed and fabricated on high resistivity silicon substrates are investigated. These CPWs exhibited transmission losses around 0.4 dB/mm at 50 GHz. In particular, temperature-dependent measurements show very low deviations. The complex relative permittivity and loss angle tangents are extracted through adequate TEM analytical modeling. It is shown that the results are affected by parasitic peaks that are intrinsically linked with the extraction of the characteristic impedance. To overcome this issue, a numerical resolution is proposed, based on a modelling of the transmission parameter S21 associated with the implementation of a bidimensionnal Newton-Raphson algorithm for the resolution of the inverse problem. Both methods give nearly identical results in terms of dielectric properties, confirming the validity and complementarity of the analytical and numerical models.

High-resolution photoinduced transient spectroscopy (HRPITS) has been employed to investigate iron-related point defects produced by electron irradiation in high-resistivity silicon. The measurements revealed 16 traps with activation energies ranging from 14 to 530 meV. From the comparison of results, obtained by the HRPITS and ESR measurements performed on the same samples, a trap positioned at Ev+500 meV was attributed to the iron-vacancy pair (Fei)V and that positioned at EV+530 meV to the vacancy complex with two iron atoms (Fei)2V. The former is found to be stable at 400°C, while the latter anneals out at this temperature similarly to the trap at EV+410 meV related to interstitial iron. As a result of the transformation of the (Fei)2V complex and reactions of the interstitial iron with native defects, new iron-related traps with activation energies of 85, 220 and 380 meV are formed.

Several silicon devices, including test structures and double-sided microstrip detectors, have been irradiated with a 900 MeV electron beam. The irradiated test structures have been used to quantify bulk and surface damage effects caused by the incident particles. Bulk-type conversion from n to p-type has been observed to occur at fluences of order 10/sup 14/ cm/sup -2/. For the damage constant /spl alpha/, a NIEL normalized value of about 3/spl times/10/sup -17/ A/cm has been obtained. The results confirm that high-energy electrons, like neutrons and protons, are very effective in creating bulk damage in silicon.

We observed the Drude response of photoexcited electrons in high resistivity silicon by using single-shot terahertz spectroscopy. In contrast to conventional optical-pump and terahertz-probe spectroscopy, this technique can significantly reduce the measurement time and repetition rate of pump pulses. As a result, the dynamics of long-lived photoexcited carriers in silicon is clearly observed without a pileup of the carriers.

Fully depleted, back-illuminated charge-coupled devices fabricated at Lawrence Berkeley National Laboratory on high-resistivity silicon are described. Device operation and technology are discussed, as well as the results on telescopes and future plans.

In this study, we report changes in the carrier concentration of high resistivity Si wafers after rapid thermal annealing (RTA) anneals measured by spreading resistance technique. Spreading resistance technique (SRP) profiles clearly show the generation of donor centers with concentrations and depth distributions comparable to those of vacancy-related centers reported in the literature. Changes of carrier concentrations as a function of RTA temperature, duration, ramp down rate, and subsequent annealing in the 800–1000 °C range are consistent with the earlier literature data. The influence of annealing ambient is also studied. Annealing in pure Ar atmosphere leads to profiles dominated by in-diffusion of vacancies generated at the surface, while annealing in oxidized ambient results in well-known profiles controlled by out-diffusion of vacancies generated in the wafer bulk. Studies of the wafers with different oxygen content show that the concentration of the generated donors is directly proportional to Oi concentration.

Multigraphene films grown by sublimation of the surface of semi-insulating 6H-SiC substrates in a vacuum have been studied. The films exhibit a semiconductor-type conductivity. A conclusion is made that this type of conduction is supposedly determined by defects present between separate graphene crystals constituting the carbon layers under study.

We show that in high-resistivity silicon bulk generation lifetime and surface generation velocity can not be measured with acceptable accuracy using a single gated diode, unless the gate length is suitably tailored. The accuracy with which bulk generation lifetime can be evaluated is, in particular, limited by nonidealities, contributing extra components to the gated-diode current, which are not accounted for in the standard extraction procedure.

Systematic and integrated physical modelling has been carried out for capacitance and current-based microscopic defect analysis techniques including the C-DLTS (capacitance-deep level transient spectroscopy), I-DLTS (current-DLTS), and TSC (thermally stimulated current). The applicability of various techniques to the characterization of neutron-irradiated high-resistivity silicon detectors has been examined and compared. C-DLTS is valid only for detectors irradiated to neutron fluences less than a few times 10 12 n/cm 2 , while there seems to be no limit for the applicability for I-DLTS or TSC. However, current-based techniques, unlike the C-DLTS, cannot distinguish minority carrier traps from majority ones. In addition, special care may have to be taken in determining the effective depletion depth for highly irradiated detectors.

We propose a chip-to-chip optical interconnection using a silicon (Si) subcarrier integrated with a long-wavelength vertical-cavity surface-emitting laser (LW-VCSEL) array. As the basic study of that, we examined the microwave and optical characteristics of the Si subcarrier. Finally, a demonstrator that mounted the four channels and 1550-nm LW-VCSEL array on the subcarrier has been shown with no kink L-I curves and with clear 2.5-Gb/s eye diagrams

PIN diodes and other test structures have been fabricated on both n- and p-type, high-resistivity, Floating-Zone (FZ) silicon substrates. Different alternative extrinsic-gettering techniques have been adopted to the purpose of meeting the required specification of a detector leakage current density lower than 1 nA/cm2. Phosphorus-doped polysilicon gettering provided the best results on n-type Si with a leakage current density lower than 0.2 nA/cm2 at 100 μm depletion width. On the contrary, devices made on p-type substrates exhibited a leakage current density two orders of magnitude higher. A proper control of the oxide charge at the silicon-silicon dioxide interface was found to be crucial in obtaining a predictable behavior of PIN diode detectors. Some degradation of the reverse leakage current has been observed after device dicing and bonding.

Transformation of radiation-induced defects in p+-n-n+ structures fabricated from highresistivity n-type silicon subjected to cyclic irradiation and annealing is investigated. The kinetic behavior of the increase in the concentration of the Ci-Oi defects is analyzed as a function of the detector fabrication process. During the second irradiation cycle a transformation of the defects, which were formed as a result of annealing of the original radiation defects, is observed. The appearance of “hidden” sources of deep center formation is revealed. It is established that the presence of a higher oxygen concentration, which arises in the samples as a result of the extended silicon oxidation process, results in a more active complex-formation of carbon-containing defects in comparison with samples with reduced oxygen content.

International audience; Low loss broad band transmission lines are of great interest for terahertz applications. To overcome high losses, Planar Goubau Lines (PGL) have been designed and fabricated on high resistivity silicon substrate. The measured loss level is typically 1dB/mm around 250GHz. The transitions are also extremely efficient for CPW-to-PGL conversion. The loss level depends on certain parameters such as length and width of the rectangular cross section or the thickness of the silicon substrate. The confinement of the electromagnetic wave will be also discussed particularly for different values of the strip's width.

We report on the measurement of the optical absorption of bulk crystalline silicon at 1550 nm. Using the photodeflection technique, absorption as low as 5 ppm/cm has been measured on a sample with a resistivity of 10 kΩ⋅cm . The absorption as a function of the resistivity has been derived for n-type silicon.

An overview of defect kinetics in high resistivity silicon is presented. A device model which gives type inversion due to the presence of deep acceptors is described.

This paper presents an original concept of a P+ guard ring realized in a 300μm depth High Resistivity Silicon Substrate (HRS) in order to reduce the substrate noise coupling in a 3D-PICS Integrated Passive Device technology. Guard rings have been designed to be a reliable and efficient protection against noise signals propagation. Case study presented in this work illustrates its significant role. In this paper, a 3D-PICS IPD test chip was studied as a first passive part prototype of a System-In-Package chip in combination with RF transceiver operating in the ISM band (863-870 MHz). Various configurations of the passive chip layout (including implementation of guard rings) have been characterized by Direct Power Injection. 3D-PICS electrical performances deduced from two-ports S-parameters are reported, as well as the guard rings efficiency measurements extracted from these S-parameters. Coupling isolation performances of the new integrated PICS components are found satisfactory.

A summary of recent progress in understanding the fundamental causes of bulk damage in high resistivity silicon detectors is given. A model based on deep acceptor states in the material appears to explain most of the experimental results. Candidates for the traps have been tentatively identified as vacancy-oxygen complexes with the aid of numerical simulations. The concentration of oxygen and carbon in the silicon is important in influencing the concentration of deep traps and may allow the possibility of improving the hardness of detectors.

Observations have been made of the behaviour of high resistivity silicon and semi-insulating gallium arsenide ionizing radiation detectors after exposure of up to 30 Mrad 60 Co photons. Results are presented on leakage current and deep level defects of the substrate material of photon damage devices. These findings have been related to the charge collection efficiency of the detectors.

The current models for bulk damage in high resistivity silicon have been reviewed. The damage constants were obtained from a global data survey. On this basis the degradation of the silicon counters in the ATLAS Inner Detector during a 10 year LHC operation is forecasted.

In this paper a multiple strip photo mixing demodulator fabricated on high resistivity silicon is described. The performance such as DC characteristics, demodulation contrast and non-linearity problem of a test sample are simulated and experimentally estimated. The experimental results exhibit a good DC charge separation and good dynamic demodulation capabilities up to 30MHz. The influence of modulation frequency and voltage on this device is also discussed. This test device corresponds to the first step towards incorporating a high resolution Time of Flight (TOF) based 3D image sensor.

This paper investigates for the first time concepts of W-band dielectric-core helix antennas which are fabricated by three-dimensional micromachining into the volume of a semiconductor (high-resistivity silicon) wafer substrate. The maximum antenna gain is achieved by free-etching the antenna but loading the core of the helical antenna with a dielectric-rod tailor-made out of the substrate, and by properly modifying the geometry of the substrate-integrated ground plane. The simulation results show that an optimized antenna concept has a return loss S11 of -22.3 dB at the nominal frequency of 75 GHz, and a 3dB-bandwidth of 2.5 GHz. For the whole band from 69 to84 GHz, the reflection coefficient is better than -10 dB. A maximum gain of 13.2 dB and a half-power beamwidth (HPBW) of smaller than 40° are obtained for a single antenna. The front to-back (F/B) ratio is better than 23.5 dB with an axial ratio of 0.94. An eight-element helix line array is demonstrated and has a maximum gain of 22.3 dB with a HPBW of 7° in the y-z plane and an F/B ratio of 23.71 dB. QC 20120730. Honorable Mention in Student Paper Competition