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The ubiquitous noise in quantum system hinders the advancement of quantum information processing and has driven the emergence of different hardware-efficient quantum error correction protocols. Among them, qubits with structured noise, especially with biased noise, are one of the most promising platform to achieve fault-tolerance due to the high error thresholds of quantum error correction codes tailored for them. Nevertheless, their quantum operations are challenging and the demonstration of their performance beyond the fault-tolerant threshold remain incomplete. Here, we leverage Schr\"odinger cat states in a scalable planar superconducting nonlinear oscillator to thoroughly characterize the high-fidelity single-qubit quantum operations with systematic quantum tomography and benchmarking tools, demonstrating the state-of-the-art performance of operations crossing the fault-tolerant threshold of the XZZX surface code. These results thus embody a transformative milestone in the exploration of quantum systems with structured error channels. Notably, our framework is extensible to other types of structured-noise systems, paving the way for systematic characterization and validation of novel quantum platforms with structured noise., Comment: 19 pages, 12 figures

High-fidelity mid-circuit measurements, which read out the state of specific qubits in a multiqubit processor without destroying them or disrupting their neighbors, are a critical component for useful quantum computing. They enable fault-tolerant quantum error correction, dynamic circuits, and other paths to solving classically intractable problems. But there are almost no methods to assess their performance comprehensively. We address this gap by introducing the first randomized benchmarking protocol that measures the rate at which mid-circuit measurements induce errors in many-qubit circuits. Using this protocol, we detect and eliminate previously undetected measurement-induced crosstalk in a 20-qubit trapped-ion quantum computer. Then, we use the same protocol to measure the rate of measurement-induced crosstalk error on a 27-qubit IBM Q processor, and quantify how much of that error is eliminated by dynamical decoupling., Comment: 7 pages, 4 figures, plus supplemental notes

Standard compilers for quantum circuits decompose arbitrary single-qubit gates into a sequence of physical X(pi/2) pulses and virtual-Z phase gates. Consequently, many circuit classes implement different logic operations but have an equivalent structure of physical pulses that only differ by changes in virtual phases. When many structurally-equivalent circuits need to be measured, generating sequences for each circuit is unnecessary and cumbersome, since compiling and loading sequences onto classical control hardware is a primary bottleneck in quantum circuit execution. In this work, we develop a hardware-assisted protocol for executing parameterized circuits on our FPGA-based control hardware, QubiC. This protocol relies on a hardware-software co-design technique in which software identifies structural equivalency in circuits and "peels" off the relevant parameterized angles to reduce the overall waveform compilation time. The hardware architecture then performs real-time "stitching" of the parameters in the circuit to measure circuits that implement a different overall logical operation. This work demonstrates significant speed ups in the total execution time for several different classes of quantum circuits.

Rapid progress in quantum technology has transformed quantum computing and quantum information science from theoretical possibilities into tangible engineering challenges. Breakthroughs in quantum algorithms, quantum simulations, and quantum error correction are bringing useful quantum computation closer to fruition. These remarkable achievements have been facilitated by advances in quantum characterization, verification, and validation (QCVV). QCVV methods and protocols enable scientists and engineers to scrutinize, understand, and enhance the performance of quantum information-processing devices. In this Tutorial, we review the fundamental principles underpinning QCVV, and introduce a diverse array of QCVV tools used by quantum researchers. We define and explain QCVV's core models and concepts -- quantum states, measurements, and processes -- and illustrate how these building blocks are leveraged to examine a target system or operation. We survey and introduce protocols ranging from simple qubit characterization to advanced benchmarking methods. Along the way, we provide illustrated examples and detailed descriptions of the protocols, highlight the advantages and disadvantages of each, and discuss their potential scalability to future large-scale quantum computers. This Tutorial serves as a guidebook for researchers unfamiliar with the benchmarking and characterization of quantum computers, and also as a detailed reference for experienced practitioners.

Randomized compiling (RC) is an efficient method for tailoring arbitrary Markovian errors into stochastic Pauli channels. However, the standard procedure for implementing the protocol in software comes with a large experimental overhead -- namely, it scales linearly in the number of desired randomizations, each of which must be generated and measured independently. In this work, we introduce a hardware-efficient algorithm for performing RC on a cycle-by-cycle basis on the lowest level of our FPGA-based control hardware during the execution of a circuit. Importantly, this algorithm performs a different randomization per shot with zero runtime overhead beyond measuring a circuit without RC. We implement our algorithm using the QubiC control hardware, where we demonstrate significant reduction in the overall runtime of circuits implemented with RC, as well as a significantly lower variance in measured observables.

Current benchmarks for mid-circuit measurements (MCMs) are limited in scalability or the types of error they can quantify, necessitating new techniques for quantifying their performance. Here, we introduce a theory for learning Pauli noise in MCMs and use it to create MCM cycle benchmarking, a scalable method for benchmarking MCMs. MCM cycle benchmarking extracts detailed information about the rates of errors in randomly compiled layers of MCMs and Clifford gates, and we demonstrate how its results can be used to quantify correlated errors during MCMs on current quantum hardware. Our method can be integrated into existing Pauli noise learning techniques to scalably characterize and benchmark wide classes of circuits containing MCMs., Comment: 6+7 pages, 3+4 figures; v2: changed notation throughout, fixed typos in theory section, added SM section on learnability

Quantum processors are now able to run quantum circuits that are infeasible to simulate classically, creating a need for benchmarks that assess a quantum processor's rate of errors when running these circuits. Here, we introduce a general technique for creating efficient benchmarks from any set of quantum computations, specified by unitary circuits. Our benchmarks assess the integrated performance of a quantum processor's classical compilation algorithms and its low-level quantum operations. Unlike existing "full-stack benchmarks", our benchmarks do not require classical simulations of quantum circuits, and they use only efficient classical computations. We use our method to create randomized circuit benchmarks, including a computationally efficient version of the quantum volume benchmark, and an algorithm-based benchmark that uses Hamiltonian simulation circuits. We perform these benchmarks on IBM Q devices and in simulations, and we compare their results to the results of existing benchmarking methods., Comment: 9 pages+appendices, 6+1 figures

We introduce binary randomized benchmarking (BiRB), a protocol that streamlines traditional RB by using circuits consisting almost entirely of i.i.d. layers of gates. BiRB reliably and efficiently extracts the average error rate of a Clifford gate set by sending tensor product eigenstates of random Pauli operators through random circuits with i.i.d. layers. Unlike existing RB methods, BiRB does not use motion reversal circuits -- i.e., circuits that implement the identity (or a Pauli) operator -- which simplifies both the method and the theory proving its reliability. Furthermore, this simplicity enables scaling BiRB to many more qubits than the most widely-used RB methods., Comment: 9 pages + appendices, 5 figures, v2: Close to published version, fixed typos in theory section

Holistic benchmarks for quantum computers are essential for testing and summarizing the performance of quantum hardware. However, holistic benchmarks -- such as algorithmic or randomized benchmarks -- typically do not predict a processor's performance on circuits outside the benchmark's necessarily very limited set of test circuits. In this paper, we introduce a general framework for building predictive models from benchmarking data using capability models. Capability models can be fit to many kinds of benchmarking data and used for a variety of predictive tasks. We demonstrate this flexibility with two case studies. In the first case study, we predict circuit (i) process fidelities and (ii) success probabilities by fitting error rates models to two kinds of volumetric benchmarking data. Error rates models are simple, yet versatile capability models which assign effective error rates to individual gates, or more general circuit components. In the second case study, we construct a capability model for predicting circuit success probabilities by applying transfer learning to ResNet50, a neural network trained for image classification. Our case studies use data from cloud-accessible quantum computers and simulations of noisy quantum computers.

Randomized benchmarking (RB) protocols are widely used to measure an average error rate for a set of quantum logic gates. However, the standard version of RB is limited because it only benchmarks a processor's native gates indirectly, by using them in composite $n$-qubit Clifford gates. Standard RB's reliance on $n$-qubit Clifford gates restricts it to the few-qubit regime, because the fidelity of a typical composite $n$-qubit Clifford gate decreases rapidly with increasing $n$. Furthermore, although standard RB is often used to infer the error rate of native gates, by rescaling standard RB's error per Clifford to an error per native gate, this is an unreliable extrapolation. Direct RB is a method that addresses these limitations of standard RB, by directly benchmarking a customizable gate set, such as a processor's native gates. Here we provide a detailed introduction to direct RB, we discuss how to design direct RB experiments, and we present two complementary theories for direct RB. The first of these theories uses the concept of error propagation or scrambling in random circuits to show that direct RB is reliable for gates that experience stochastic Pauli errors. We prove that the direct RB decay is a single exponential, and that the decay rate is equal to the average infidelity of the benchmarked gates, under broad circumstances. This theory shows that group twirling is not required for reliable RB. Our second theory proves that direct RB is reliable for gates that experience general gate-dependent Markovian errors, using similar techniques to contemporary theories for standard RB. Our two theories for direct RB have complementary regimes of applicability, and they provide complementary perspectives on why direct RB works. Together these theories provide comprehensive guarantees on the reliability of direct RB.

Randomized benchmarking (RB) protocols are the most widely used methods for assessing the performance of quantum gates. However, the existing RB methods either do not scale to many qubits or cannot benchmark a universal gate set. Here, we introduce and demonstrate a technique for scalable RB of many universal and continuously parameterized gate sets, using a class of circuits called randomized mirror circuits. Our technique can be applied to a gate set containing an entangling Clifford gate and the set of arbitrary single-qubit gates, as well as gate sets containing controlled rotations about the Pauli axes. We use our technique to benchmark universal gate sets on four qubits of the Advanced Quantum Testbed, including a gate set containing a controlled-S gate and its inverse, and we investigate how the observed error rate is impacted by the inclusion of non-Clifford gates. Finally, we demonstrate that our technique scales to many qubits with experiments on a 27-qubit IBM Q processor. We use our technique to quantify the impact of crosstalk on this 27-qubit device, and we find that it contributes approximately 2/3 of the total error per gate in random many-qubit circuit layers., Comment: 15 pages + appendices. v2: Corrected error in Section IIIA step 3 + minor edits. v3: Added new theory results

Quantum simulation promises to address many challenges in fields ranging from quantum chemistry to material science, and high-energy physics, and could be implemented in noisy intermediate-scale quantum devices. A challenge in building good digital quantum simulators is the fidelity of the engineered dynamics given a finite set of elementary operations. Here we present a framework for optimizing the order of operations based on a geometric picture, thus abstracting from the operation details and achieving computational efficiency. Based on this geometric framework, we provide two alternative second-order Trotter expansions, one with optimal fidelity at a short time scale, and the second robust at a long time scale. Thanks to the improved fidelity at different time scale, the two expansions we introduce can form the basis for experimental-constrained digital quantum simulation.