Search

As diamond possesses only deep dopants, certain conventional physics and characterization methods are not applicable to diamond devices, owing to the explicit or implicit assumption of shallow dopants. To resolve this limitation, the capacitance–voltage (C–V) characteristics of metal–insulator–semiconductor (MIS) capacitors formed on a semiconductor substrate with deep and compensating dopants were successfully formulated. Based on these equations, methods for accurately estimating the MIS capacitor properties were developed and validated through their application in the analysis of an actual MIS capacitor formed on a boron-doped hydrogen-terminated diamond substrate. The high-frequency C–V characteristic of the capacitor exhibited a prominent dip specific to deep dopants. However, the dip depth was considerably shallower than theoretically expected. This C–V characteristic was accurately reproduced theoretically, assuming the presence of a surficial diamond layer that contains acceptors with an activation energy of 0.23 eV, which is less than the value 0.37 eV for boron, and has a thickness of the extrinsic Debye length (40 nm in this study) or larger. The insulator charge of the MIS capacitor was estimated as −4.6 × 1012 cm−2 in units of electronic charge, which is sufficiently large to induce two-dimensional hole gas. The interface-state density was 1.4 × 1012 cm−2 eV−1 for interface-state energies of 0.3–0.5 eV above the valence band maximum. Hence, the proposed methodology and the possible presence of the reduced activation energy layer will guide the development of diamond-based devices. [ABSTRACT FROM AUTHOR]

The influence of Al2O3 atomic-layer deposition (ALD) temperature on the electric characteristics of Al / A l 2 O 3 / ( 2 ¯ 01) β-Ga2O3 capacitors was investigated focusing on the positive-bias instability (PBI) of the capacitors. The current in the capacitors increased with ALD temperature, mostly because of the reduced energy barrier height for the electron field emission from the substrate and less negative Al2O3 charge, as revealed by the analysis conducted assuming a space-charge-controlled field emission process. The PBI tests were conducted for cumulative voltage stressing times vastly ranging from 3 × 10−6 to 4 × 105 s. The capacitance–voltage (C–V) characteristics of the capacitors for an ALD temperature of 100 °C displayed negative shifts in the middle of voltage stressing, unlike those for the other ALD temperatures. The bias stability of the capacitors was found to be considerably improved by high-temperature (450 °C) ALD. Additionally, the C–V characteristic shifts caused by the voltage stressing were theoretically reproduced quite accurately, assuming a model proposed in this study. In the simulations, the trap distributions in the Al2O3 films were assumed to be uniform both spatially and energetically. Importantly, the experimental results for various stressing voltages were excellently fitted by the simulations that assumed the same trap distribution. The trap densities in the Al2O3 films thus estimated reduced from 1.2 × 1020 to 2.2 × 1019 cm−3 eV−1 for ALD temperatures of 100–450 °C. This reduction in the trap densities was a major cause of the bias stability enhancement for high-temperature ALD. Moreover, the trap density as a function of ALD temperature qualitatively agreed with the aforementioned Al2O3 charge generated by the current measurements. This agreement provides a strong basis for the validity of the PBI model proposed in this study. [ABSTRACT FROM AUTHOR]

The current conduction in negatively biased metal/Al2O3/diamond capacitors with various gate materials and diamond surface terminations was comprehensively characterized by assuming a space-charge-controlled field emission (SCC-FE) process, yielding the following results. The current-feeding carriers were field-emitted from the electrode that had a barrier height lower than that of the opposing electrode. Specifically, in an Au-gate oxygen-terminated diamond capacitor, holes were likely to be emitted from the Al2O3/diamond interface states, whereas, in Al-gate oxygen-terminated, Au-gate hydrogen-terminated, and Al-gate hydrogen-terminated diamond capacitors, electrons were emitted from the gate. The barrier heights at the Al/Al2O3 and Au/Al2O3 interfaces were estimated as 1.6–1.7 and 2.8 eV, respectively. However, the analysis of the hole emission from the interface states is left for future studies. Although the substrate of the oxygen-terminated diamond capacitor remained weakly depleted even for highly negative gate voltages, the conduction current was observed as mentioned earlier. To analyze the mechanism for this conduction, the diffusion and drift currents in the depleted substrate were quantitatively estimated, ascribing the current conduction to the diffusion current. As these results could not be obtained by using the conventional graphical methods based on model-specific plots, such as the Fowler–Nordheim and Poole–Frenkel plots, the SCC-FE analysis proved to be a powerful tool for investigating the current conduction in metal-insulator-semiconductor capacitors. [ABSTRACT FROM AUTHOR]

As previously reported, postdeposition annealing at 800 °C and higher simultaneously crystallizes atomic-layer-deposited (ALD) Al2O3 films and reduces the current in Al/ALD-Al2O3/(0001) GaN capacitors by two orders of magnitude. This current reduction is caused by the enhancement of conduction band offset from 1.4 to 1.8 eV, as revealed by the space-charge-controlled field emission analysis. Selected area electron diffraction (SAED) patterns demonstrate that the crystallized films consist of twinned (111)-oriented cubic γ-Al2O3 with an epitaxial relation of Al2O3 ⟨ 0 1 ¯ 1 ⟩ ∥ GaN ⟨ 2 1 ¯ 1 ¯ 0 ⟩. The SAED patterns additionally include spots that are specific to triaxially tripled γ-Al2O3. The aforementioned epitaxy is due to the similarity of hexagonal close-packed sublattices between oxygen on a (111) γ-Al2O3 plane and nitrogen on a (0001) GaN plane. However, the hexagonal close-packed lattice constant of γ-Al2O3 is 12% smaller than that of GaN, necessitating domain matching epitaxy. The thickness of the interfacial transition layer caused by the large misfit is estimated to be thinner than four monolayers of oxygen sublattice, by using the methodology developed here. Based on these results, the effect of Al2O3 crystallinity on the characteristics of Al2O3/GaN capacitors, such as conduction current, dielectric breakdown, interface states, and bias instability, was comprehensively captured. According to x-ray diffraction analyses, Al2O3 films crystallize at 700 °C, which is ∼100 °C lower than the threshold temperature estimated by transmission electron microscope observations. This difference was possibly caused by locally crystallized Al2O3 films, as confirmed by the slightly reduced current. These findings form a basis for improving ALD-Al2O3 films as gate insulator. [ABSTRACT FROM AUTHOR]

A dynamic space-charge-controlled field emission (SCC-FE) model that considers temporal insulator charge variations caused by voltage stress is developed for analyzing the current conduction in insulators in the entire voltage range of measurement, yielding good agreement between experiments and simulations. The usage of prestressed samples in this analysis is essential for accurately estimating the electron affinities of insulators, yielding 1.65 and 1.93 eV as the estimates for Al2O3 films formed on GaN by atomic-layer deposition (ALD) at 200 and 450 °C, respectively, and 1.65 and 1.83 eV for those on SiO2/Si, respectively. Through the bias instability analysis using the method developed here, the voltage-stress tolerance of both Si and GaN metal–insulator–semiconductor (MIS) capacitors with ALD Al2O3 films was found to be enhanced by the high-temperature (450 °C) ALD. The analysis also revealed the fact that the voltage-stress-induced flatband voltage shift of GaN capacitors with the high-temperature Al2O3 films is mainly caused by the Al2O3 charges near the substrate, hence providing a clue to even better bias stability of the GaN capacitors. With possible applications to other wide-bandgap semiconductor (WBGS) capacitors, the dynamic SCC-FE analysis developed here will play an essential role in analyzing not only gate insulator characteristics but also many reliability issues of various WBGS MIS field-effect transistors. [ABSTRACT FROM AUTHOR]

Electric dipoles at a metal-gate/Al2O3 interface are found to control the current conduction in negatively biased Al2O3 metal-insulator-semiconductor (MIS) capacitors by effectively increasing the Al2O3 electron affinity near the gate and thereby reducing the barrier height against electron field emission from the gate. By carrying out space-charge-controlled field emission analysis, the Al2O3 effective electron affinity in Al-gate capacitors was found to be larger than that for the Au gate by 0.38 eV, and the value for the Ni gate was similar to that for the Au gate. The cross-sectional transmission-electron-microscope images of the samples revealed the presence of an approximately 3-nm-thick layer intervening between the Al gate and the Al2O3 film. This layer is likely to have formed Al/Al2O3 interfacial dipoles that caused the aforementioned shift of the Al2O3 effective electron affinity. It was also confirmed that the conventional Fowler–Nordheim tunneling analysis yields remarkably erroneous results under the presence of these dipoles. These findings not only form the basis for investigating the band alignment of metal-gate MIS capacitors, but also alert us to a possibility of unexpectedly large leakage currents in negatively biased metal-gate MIS field-effect transistors. [ABSTRACT FROM AUTHOR]

To accurately analyze the deep states at the insulator/wide-bandgap semiconductor interface, this study reassessed and improved the conventional photoassisted capacitance–voltage (PACV) method. First, as previously pointed out, the illumination time under depletion should be long enough that the voltage shift caused by interface-state depopulation (in n-type semiconductors) saturates. Excessive illumination, however, causes insulator charging, thereby apparently increasing estimated values. To solve this problem, this study proposes to measure reference characteristics just after postillumination ones. Secondly, the postillumination measurements should be started without delay after turning off the light or may be carried out with the samples being illuminated. Thirdly, the depletion should be deep enough that the magnitude of band bending in the substrate at the beginning of the postillumination measurements is larger than 1 V. This guideline considerably relaxes a previous one that required a band bending of bandgap or larger. Furthermore, this study developed a method for compensating the interface-state depopulation (in n-type) during the reference measurements, in which the depopulation causes the so-called stretch-out. The results thus obtained from an Al/Al2O3/GaN capacitor agreed fairly well with those by a recently developed transient photoassisted capacitance method, supporting the validity of both methods. Being less sensitive to the gate-insulator charging, the advanced PACV method developed here has an advantage over the transient method and, therefore, will help advance the technology for fabricating high-performance, high-reliability insulator/wide-bandgap semiconductor insulators. [ABSTRACT FROM AUTHOR]

Atomic-layer-deposited (ALD) Al2O3 films are the most promising surface passivation and gate insulation layers in non-Si semiconductor devices. Here, we carried out an extensive study on the time-dependent dielectric breakdown characteristics of ALD-Al2O3 films formed on homo-epitaxial GaN substrates using two different oxidants at two different ALD temperatures. The breakdown times were approximated by Weibull distributions with average shape parameters of 8 or larger. These values are reasonably consistent with percolation theory predictions and are sufficiently large to neglect the wear-out lifetime distribution in assessing the long-term reliability of the Al2O3 films. The 63% lifetime of the Al2O3 films increases exponentially with a decreasing field, as observed in thermally grown SiO2 films at low fields. This exponential relationship disproves the correlation between the lifetime and the leakage current. Additionally, the lifetime decreases with measurement temperature with the most remarkable reduction observed in high-temperature (450 °C) O3-grown films. This result agrees with that from a previous study, thereby ruling out high-temperature O3 ALD as a gate insulation process. When compared at 200 °C under an equivalent SiO2 field of 4MV/cm, which is a design guideline for thermal SiO2 on Si, high-temperature H2O-grown Al2O3 films have the longest lifetimes, uniquely achieving the reliability target of 20 years. However, this target is accomplished by a relatively narrow margin and, therefore, improvements in the lifetime are expected to be made, along with efforts to decrease the density of extrinsic Al2O3 defects, if any, to promote the practical use of ALD Al2O3 films. [ABSTRACT FROM AUTHOR]

In this article, the normally- OFF oxidized Si-terminated (C–Si) diamond metal–oxide–semiconductor field-effect transistors (MOSFETs) with as-deposited 0.5-nm silicon on diamond annealed at high temperature as the subsurface p-channel were presented for the first time. A novel method utilizing both a metal mask to realize the regrown heavily boron-doped (001) diamond layer first (p+-diamond-first) and a molecular beam deposition (MBD) method to procure atomic-scale silicon deposition was achieved. Scanning transmission electron microscopy (STEM) and energy-dispersive X-ray spectroscopy (EDS) element mapping results suggest that the C–Si diamond/Al2O3 interface is quite continuous and atomically flat. A remarkably high threshold voltage (${V}_{\text{TH}}$) of −10 V and a maximum drain current density (${I}_{D\_{}{\text{MAX}}}$) of −156 mA/mm are simultaneously achieved in the fabricated devices. The devices with different source and drain (S/D) distances ($L_{\text{SD}}$) deliver robust ${V}_{\text{TH}}$ results and feature low OFF-state S/D leakage current $\vert {I}_{\text{leakage}}\vert $ of ~ $6\times10$ −6 mA/mm at ${V}_{\text{GS}}$ = 0 V. The extracted field-effect mobility is as high as 127 cm2 $\cdot \text{V}$ −1 $\cdot \text{s}$ −1 and the interface state density is as low as $4.35\times10$ 12 eV−1 $\cdot $ cm−2. These competitive results reveal that this first attempt of employing the combination of p+-diamond-first and MBD approaches promotes the integration of the advanced silicon manufacturing process with wide bandgap diamond material for power applications. [ABSTRACT FROM AUTHOR]

The effect of dopant profile engineering on planar MOSFETs fabricated using laser spike annealing (LSA) activation is examined. Results suggest 10 percent improvement in device performance as compared to conventional LSA devices.

A novel laser thermal process that dramatically enhances laser exposure windows by controlling the heating process in a self-limiting way is developed. Key technology is realized by introducing a new process combination of premorphization implantation and a heat absorber with a phase switch layer, and by optimizing them.

This letter reports the successful demonstration of large-current and high-voltage (001) vertical-type two-dimensional hole gas (2DHG) diamond trench metal-oxide-semiconductor field-effect transistors (MOSFETs) with a p−-drift layer. The fabricated transistor demonstrated a maximum drain current density of 210 mA/mm, a field-effect-mobility of 61 cm2V−1s−1, and a specific on-resistance of 23 $\text{m}\Omega $ cm2. Moreover, a high breakdown voltage of 580 V with a gate-drain length of 10 $\mu \text{m}$ was obtained, which is the highest value reported for a vertical-type diamond MOSFET to date. These characteristics indicate that a vertical-type diamond MOSFET using a p−-drift layer may be used to realize a p-channel power device with a high breakdown voltage and low on-resistance. [ABSTRACT FROM AUTHOR]

β-Ga2O3 is gaining increasing attention from power device engineers owing to its wide bandgap and fabrication potential of low-cost, large-diameter substrates. Atomic-layer-deposited (ALD) Al2O3 has application potential for the gate insulation and surface passivation of β-Ga2O3 devices, which cannot incorporate a well-established SiO2/Si system. To improve the device performance and reliability, the effect of postdeposition annealing (PDA) on the gate insulation characteristics of Al/ALD-Al2O3/(001) β-Ga2O3 capacitors was comprehensively investigated. As in previous studies, PDA at 700 °C and higher sharply reduced the capacitor leakage current by three orders of magnitude. This threshold temperature was 100 °C lower than that for GaN devices. Space-charge-controlled field emission analysis revealed that the current reduction was achieved via conduction-band-offset enhancement from 1.45 to 2.2 eV. These changes were caused by Al2O3 crystallization, which started at 650 °C according to an x-ray diffraction analysis. Selective-area electron diffraction (SAED) patterns showed that the crystallized films comprised twinned γ-Al2O3, wherein the (111) planes are parallel to the sawtooth β-Ga2O3 (101) planes with epitaxial relations of γ-Al2O3 [ 0 1 ¯ 1 ] || β-Ga2O3 [010] and γ-Al2O3 [ 01 1 ¯ ] || β-Ga2O3 [010]. This epitaxy was realized by three-dimensional oxygen sublattice matching with relatively small misfits of less than 1%, 1%, and 8% along the γ-Al2O3 [ 2 1 ¯ 1 ¯ ] , [111], and [ 01 1 ¯ ] directions, respectively. Furthermore, the SAED patterns displayed diffraction spots specific to triaxially tripled γ-Al2O3. This is yet to be identified as δ-Al2O3. Contrary to expectations, PDA magnified the bias instability of β-Ga2O3 capacitors, supposedly owing to the Al2O3 and Ga2O3 solid-solution reaction, which contrasts with the previous significant improvement in GaN capacitors. However, PDA negligibly affected the β-Ga2O3 capacitor interface characteristics. This result also contrasts sharply with the previous results obtained for GaN capacitors that experienced a PDA-induced increase in both interface states and flat-band voltage. This apparent thermal stability of Al2O3/(001) β-Ga2O3 interface can be ascribed to the aforementioned small lattice misfit at the γ-Al2O3/(101) β-Ga2O3 interface, which contrasts with the 12% misfit at the γ-Al2O3/(0001) GaN interface. These findings form the foundation for developing technologies to enhance the performance and reliability of ALD-Al2O3/β-Ga2O3 devices. Specifically, based on them, a guideline for reducing the bias instability is proposed. [ABSTRACT FROM AUTHOR]

Large reverse leakage current in p-n junctions can be explained in terms of the local Zener effect around small precipitates at a region of high field in the depletion layer. The electric field and temperature dependence of local Zener probability are used to explain a very large leakage current. Lowering of the local electric field reduces the local Zener probability. A new method for Zener probability reduction is described.

The need for chemical contamination control for future LSI's is investigated by considering device failure mechanisms. The allowable contamination density is calculated by deducing relationships between the contamination density and resultant defect density from experimental results. In the calculations LSI failures are classified into two groups according to the characteristics of failure-producing defects: macrotype and microtype. The former defects are macroscopic and fatal: a single defect causes a failure. A stricter contamination control is required for smaller devices similar to that predicted by conventional yield theory. This is due to increasing chip area. By contrast the latter defects are of atomic size, and a single defect is not fatal: devices fail when the defect density exceeds some threshold value. Transconductance degradation in MOS transistors due to interface traps and the resultant SRAM operation error is proposed as an example. The threshold defect (or contamination) density for the failure could be 1 X 10 to the eleventh power cm to the -2 in this model. The allowable contamination density abruptly decreases for a minimum pattern size smaller than 0.1 micrometer. This is due to increasing fluctuations of defect density in component devices. This failure might cause a bottleneck in developing gigabit memories.

Atomic force microscopy and current imaging tunneling spectroscopy were used to investigate natural oxide growth on silicon facets. The results showed that natural oxide growth on some special high-index-orientation silicon facets in the vicinity of {111} was smaller than that on the other silicon facets.

The Al2O3 film formed using an atomic layer deposition (ALD) method with trimethylaluminum as Al precursor and H2O as oxidant at a high temperature (450 °C) effectively passivates the p-type surface conduction (SC) layer specific to a hydrogen-terminated diamond surface, leading to a successful operation of diamond SC field-effect transistors at 400 °C. In order to investigate this excellent passivation effect, we carried out an isotope analysis using D2O instead of H2O in the ALD and found that the Al2O3 film formed at a conventional temperature (100 °C) incorporates 50 times more CH3 groups than the high-temperature film. This CH3 is supposed to dissociate from the film when heated afterwards at a higher temperature (550 °C) and causes peeling patterns on the H-terminated surface. The high-temperature film is free from this problem and has the largest mass density and dielectric constant among those investigated in this study. The isotope analysis also unveiled a relatively active H-exchange reaction between the diamond H-termination and H2O oxidant during the high-temperature ALD, the SC still being kept intact. This dynamic and yet steady H termination is realized by the suppressed oxidation due to the endothermic reaction with H2O. Additionally, we not only observed the kinetic isotope effect in the form of reduced growth rate of D2O-oxidant ALD but found that the mass density and dielectric constant of D2O-grown Al2O3 films are smaller than those of H2O-grown films. This is a new type of isotope effect, which is not caused by the presence of isotopes in the films unlike the traditional isotope effects that originate from the presence of isotopes itself. Hence, the high-temperature ALD is very effective in forming Al2O3 films as a passivation and/or gate-insulation layer of high-temperature-operation diamond SC devices, and the knowledge of the aforementioned new isotope effect will be a basis for further enhancing ALD technologies in general. [ABSTRACT FROM AUTHOR]

Use of two-dimensional hole gas (2DHG), induced on a hydrogenated diamond surface, is a solution to overcoming one of demerits of diamond, i.e., deep energy levels of impurities. This 2DHG is affected by its environment and accordingly needs a passivation film to get a stable device operation especially at high temperature. In response to this requirement, we achieved the high-reliability passivation forming an Al2O3 film on the diamond surface using an atomic-layer-deposition (ALD) method with an H2O oxidant at 450 °C. The 2DHG thus protected survived air annealing at 550 °C for an hour, establishing a stable high-temperature operation of 2DHG devices in air. In part, this achievement is based on high stability of C-H bonds up to 870 °C in vacuum and above 450 °C in an H2O-containing environment as in the ALD. Chemically, this stability is supported by the fact that both the thermal decomposition of C-H bonds and reaction between C-H bonds and H2O are endothermic processes. It makes a stark contrast to the instability of Si-H bonds, which decompose even at room temperature being exposed to atomic hydrogen. In this respect, the diamond 2DHG devices are also promising as power devices expectedly being free from many instability phenomena, such as hot carrier effect and negative-bias temperature instability, associated with Si devices. As to adsorbate, which is the other prerequisite for 2DHG, it desorbed in vacuum below 250 °C, and accordingly some new adsorbates should have adsorbed during the ALD at 450 °C. As a clue to this question, we certainly confirmed that some adsorbates, other than those at room temperature, adsorbed in air above 100 °C and remained at least up to 290 °C. The identification of these adsorbates is open for further investigation. [ABSTRACT FROM AUTHOR]

We present a miniaturized vertical-type two- dimensional hole gas (2DHG) diamond metal-oxide-semiconductor field-effect transistor (MOSFET) by adopting a gate-source overlapping structure. We developed a 2- $\mu \text{m}$ -wide trench and disposed a part of the gate electrode to overlap the Al2O3 insulator film on the source electrode to eliminate the space between source and gate electrode. We obtained the maximum drain current density of ${I}_{\text {D}} =12800$ A/cm2 at ${V}_{\text {DS}} = -50$ V and the specific on-resistance of ${R}_{\text {ON}}=3.2\,\,\text{m}\Omega $ cm2 at ${V}_{\text {DS}} = -10$ V and confirmed their improvement by the miniaturization of devices and reduction of source to gate resistance. In addition, the drain current on/off ratio was 7 orders magnitude even at 200 °C with the formation of a highly concentrated, thick nitrogen-doped layer as the current blocking layer. [ABSTRACT FROM AUTHOR]

Large-scale integrations (LSIs) are facing an ever-growing problem of device variability. One of the origins that cause the variability is line-width roughness (LWR) caused by line edge roughness (LER). Accurate characterization of the LWR plays an essential role in controlling the LWR. To do this, we report a methodology, named the “assembly method,” that enables to analyze LWR statistics beyond the conventional correlation length limit, basing on the previous “patchwork” method and recent discrete power spectral density (PSD) method. The methodology virtually assembles a long line by gathering line segments that are randomly scattered on a single line or equally processed different lines. The virtual lines are repeatedly assembled by randomly changing the combination of the segments and the order of the gathered segments while permitting overlaps of the segments between the assembled lines. Squared Fourier transforms of their widths are averaged over the assembled lines to obtain the PSD. By these steps, the statistical noise, which is inherent to experimental PSDs, is markedly reduced. Furthermore, to extract LWR statistics by comparing experimental and theoretical PSDs, we derived an analytic formula of the assembled-line PSD. In the derivation, the randomness of the segment collections played a key role. The PSDs calculated using the formula almost completely fitted experimental PSDs that were obtained by the assembly method. The parameters used in the best-fitted calculation revealed that the photoresist LWR of this study contained a component that had a correlation length of 2780 nm in addition to the previously reported LWR of 35 nm. The LWR variance of the component accounted for approximately 10% of the total variance. The formula also enabled us to evaluate the accuracy of experimentally obtained averages of widths. We find two distinct features in the PSDs by the assembly method. One is the oscillatory structure that shows up in the case when the correlation length is larger than half the length of the segments. A trace of this structure was actually observed in the experimental PSDs of this study. The other is the spikes that are periodically observed as a function of wave number. The spikes originate from a nonstochastic width variation that exists in all the segments in common. Their intensity is proportional to the number of gathered segments in the assembled lines. Because the spikes are excluded from the analysis, the LWR parameters determined by the assembly method are not affected by the nonstochastic variation, unlike the conventional methods. By all these results, we confirm that the assembly method of this study extends the upper limit of analyzable correlation lengths by a factor of approximately 20 and enhances the accuracy as well. This feature also has a practical significance that the widely observed LWR with a correlation length of approximately 35 nm can be analyzed by the assembly method using a conventional critical-dimension scanning-electron-microscope, without resorting to a specially designed one. Accordingly, the method will be a key tool for investigating LER and LWR in developing and manufacturing LSIs. It will also help analyze other stochastic processes in many research and development settings. [ABSTRACT FROM AUTHOR]

We propose an experimental method of determining the equivalent oxide thickness (EOT) of gate insulators based on the principle that the capacitance associated with the bandbendings in the Si substrate and the gate (Si capacitance) depends only on the Si surface field. To do this we experimentally obtained the Si surface field by using the capacitance-voltage (CV) integration method, and we used x-ray reflectometry to measure the physical thickness of thermal oxides. We then determined the relationship between the Si capacitance and the Si surface field. The relationship among the Si capacitance, the Si surface field, the EOT, and gate voltage minus the flatband voltage was also experimentally obtained. From these two relationships, we produce ideal CV curves for any given EOT and determined EOTs in such a way that the ideal CV curves fit best with the experimental results. Accordingly, our method is free of errors that accompany modeling the quantum mechanics of the gate electrode and Si substrate, and any errors that it does contain are independent of the film thickness. We further simplified the method for practical application by approximating the above relationships using rational polynomials. The results obtained by this simplified method were in good agreement with the experiments for the whole range of thicknesses. In contrast, the conventional quantum mechanical simulators produced C V curves that showed no small difference from the measured ones in the case of thin oxides in the 1-nm-thick range, and led to an overestimate of the EOT. Our method of EOT derivation provides an important basis for developing high-performance metal-oxide-semiconductor transistors. [ABSTRACT FROM AUTHOR]