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Semiconductor technology is currently facing the challenge of processing structures with nanometer scale openings and high aspect ratios (HAR) in order to enable the manufacture of 3D nano-devices like FINFETs, 3D-NAND cells and DRAM capacitors. Simultaneously, process control has been pushed towards sub-nanometer dimensions as 1nm variation starts to impact device performance. These requirements pose a growing challenge to wet processing inside nanometer scale openings in HAR structures of advanced 3D devices. Top to bottom etch uniformity with nanometer etch control has become a paramount necessity. High selectivity silicon etch is a critical process for 3D-NAND. Typical silicon wet etch processes have very high selectivity towards silicon dioxide. Even a monolayer of silicon dioxide can affect the silicon etch rate. Dissolved oxygen (DO) has become a key aspect during silicon etching. The dissolved oxygen can react with the exposed silicon creating silicon dioxide slowing the silicon etch. In our paper, we specifically looked at the etching of poly Si by tetramethylammonium hydroxide (TMAH) and how the etch rate is affected by DO in the solution. Figure 1a shows experimental results of etching a blanket poly Si wafer depending on the oxygen in the environment: normal air or pure nitrogen. Even though the TMAH is dispensed with a low amount of DO, as it flows across the wafer it can absorb or desorb oxygen to/from the atmosphere and accordingly change the center to edge etch rate considerably. In order to test if the hypothesis was correct, we modeled the DO concentration in the TMAH solution and predicted the DO profile inside HAR structures. Figure 1c shows the plan for modeling the DO in order to predict the etch rate variability: a liquid flow model predicts the temperature and DO across the wafer then this model feeds into an additional model for the DO concentration inside the HAR feature. These models then report the etch rate as a function of wafer position and depth in feature, so long as the etch rate as a function of temperature and DO is known. Table 1 shows the equations for the wafer surface liquid model. Equation 1 calculates the temperature and volumetric flow rate across the wafer and equation 2 uses the results of equation 1 to calculate the DO concentration. Table 2 shows the chemical reactions and rate equations for modeling the DO concentration inside a HAR feature, where the DO was consumed as it diffuses down into the feature and reacts with the poly Si. The rate of reaction 1b is assumed to be much faster than 1a, so the important rate equations are 1a, 2, and 3 with their associated rate constants. Figure 1b shows the results of the wafer surface liquid model in predicting the DO concentration and resulting etch rate across the wafer. The process environment O2 was varied in which the atmosphere is either 0.1% O2, standard 20% O2, or a carefully controlled 6% O2 chosen to maintain a constant DO in the TMAH across the wafer, even with temperature variation. However as we will show in the full paper, center to edge etch rate uniformity is insufficient for good process control, as DO consumption within HAR features causes very different etch rates between the top and bottom of the HAR structure. We will then show that this difficulty can be solved by using a much more powerful oxidizer than DO such as H2O2, ensuring a uniform etch rate across the HAR. Figure 1

This paper discusses the defect density detection and analysis methodology using advanced optical wafer inspection capability to enable accelerated development of a DSA process/process tools and the required inspection capability to monitor such a process. The defectivity inspection methodologies are optimized for grapho epitaxy directed self-assembly (DSA) contact holes with 25 nm sizes. A defect test reticle with programmed defects on guide patterns is designed for improved optimization of defectivity monitoring. Using this reticle, resist guide holes with a variety of sizes and shapes are patterned using an ArF immersion scanner. The negative tone development (NTD) type thermally stable resist guide is used for DSA of a polystyrene- b -poly(methyl methacrylate) (PS- b -PMMA) block copolymer (BCP). Using a variety of defects intentionally made by changing guide pattern sizes, the detection rates of each specific defectivity type has been analyzed. It is found in this work that to maximize sensitivity, a two pass scan with bright field (BF) and dark field (DF) modes provides the best overall defect type coverage and sensitivity. The performance of the two pass scan with BF and DF modes is also revealed by defect analysis for baseline defectivity on a wafer processed with nominal process conditions.

To make sure a baseline process will be ready for the evaluation of the NXE:3300, imec evaluates promising new EUV resist materials with regards to imaging, process window and line width roughness (LWR) performance. From those screening evaluations, highest performing materials meeting dose sensitivity requirements are selected to be installed on the coat/develop track. This work details the process optimization results of the different selected resist platforms with regards to full wafer processing. Evaluations are executed on the ASML NXE:3100 equipped with a laser-assisted discharge produced plasma source from XTREME technologies, and interfaced to a TEL CLEAN TRACKTM LITHIUS ProTM -EUV.

Previously, fundamental evaluations of the Extreme Ultra Violet (EUV) lithography process have been conducted using the CLEAN TRACK ACT™ 12 coater/developer with the ASML EUV Alpha Demo Tool (ADT) at imec. In that work, we confirmed the basic process sensitivities for the critical dimension (CD) and defectivity with EUV resists. Ultimate resolution improvements were examined with TBAH and FIRM™ Extreme. Moving forward with this work, the latest inline cluster is evaluated using the ASML NXE:3100 pre-production EUV scanner and the CLEAN TRACK™ LITHIUS Pro™ -EUV coater/developer. The imec standard EUV baseline process has been evaluated for manufacturability of CD uniformity control based on half pitch (HP) 27nm and ultimate resolution studies focusing on HP 22nm. With regards to the progress of the improvement for EUV processing, we confirmed the effectiveness of several novel concepts: FIRM™ Extreme10 showed increase in ultimate resolution and improvement in line width roughness (LWR) and process window; Tokyo Electron LTD. (TEL) smoothing process for roughness reduction showed 17% improvement for line and space (L/S) patterns; and finally the new dispense method reduced patterned wafer defectivity by over 50%.

In order to further understand the processing sensitivities of the EUV resist process, TEL and imec have continued their collaborative efforts. For this work, TEL has delivered and installed the state of the art, CLEAN TRACK™ LITHIUS Pro™ -EUV coater/developer to the newly expanded imec 300mm cleanroom in Leuven, Belgium. The exposures detailed in this investigation were performed off-line to the ASML EUV Alpha Demo Tool (ADT) as well as on the inline ADT cluster with CLEAN TRACK™ ACT™ 12 coater/developer. As EUV feature sizes are reduced, is it apparent that there is a need for more precise processing control, as can be demonstrated in the LITHIUS Pro™ -EUV. In previous work from this collaboration1, initial investigations from the ACT™ 12 work showed reasonable results; however, certainly hardware and processing improvements are necessary for manufacturing quality processing performance. This work continues the investigation into CDU and defectivity performance, as well as improvements to the process with novel techniques such as advanced defect reduction (ADR), pattern collapse mitigation with FIRM™Extreme and resolution improvement with tetrabutylammoniumhydroxide (TBAH).

EUV lithography is one of the most promising technologies for the fabrication of beyond 30nm HP generation devices. However, it is well-known that EUV lithography still has significant challenges. A great concern is the change of resist material for EUV resist process. EUV resist material formulations will likely change from conventional-type materials. As a result, substrate dependency needs to be understood. TEL has reported that the simulation combined with experiments is a good way to confirm the substrate dependency. In this work the application of HMDS treatment and SiON introduction, as an underlayer, are studied to cause a footing of resist profile. Then, we applied this simulation technique to Samsung EUV process. We will report the benefit of this simulation work and effect of underlayer application. Regarding the etching process, underlayer film introduction could have significant issues because the film that should be etched off increases. For that purpose, thinner films are better for etching. In general, thinner films may have some coating defects. We will report the coating coverage performance and defectivity of ultra thin film coating.

In this paper we summarize our investigations into processing capability on the CLEAN TRACK TM LITHIUS Pro TM - i & TWINSCAN TM NXT:1950i litho cluster. Process performance with regards to critical dimension (CD) uniformity and defectivity are investigated to confirm adherence to ITRS 1 roadmaps specifications. Additionally, a study of wafer backside particle contamination is performed to understand the implications towards processing. As wafer stage chuck cleaning on the scanner will require considerable down time, this study is necessary to understand the requirements for manufacturability. Previous work from our collaboration succeeded in a processing improvement of over 80% in across wafer CD variation by implementing the newest post exposure bake (PEB) plate design 2 and optimized developer process. With regards to defectivity, the use of the advanced defect reduction (ADR) process with an optimized bevel cut of the resist allowed the use of a high contact angle material process which is required for optimal immersion hood performance. In this work, further optimization of the process with consideration of the design concept of the TWINSCAN TM NXT:1950i and hardware modifications on the CLEAN TRACK TM LITHIUS Pro TM - i will be performed. From this investigation, it is expected to understand the process capability of 38nm CD uniformity using novel developer hardware. Additionally, the defectivity challenges for processing with higher scan speeds in combination with the hydrophobicity of the coating materials and edge cut strategy will be clarified. Initial evaluation results are analyzed to understand the correlation of various types and densities of contaminates on the backside of the wafer to the formation of wafer stage chuck focus spots (FS). Focus spots are a localized irregular focus and leveling height.

This work is the summary of improvements in processing capability implemented and tested on the LITHIUS ProTM -i / TWINSCANTM XT:1950Hi litho cluster installed at ASML's development clean room at Veldhoven, the Netherlands. Process performance with regards to CD uniformity (CDU) and defectivity are investigated to confirm adherence to ITRS roadmaps specifications. Specifically, imaging capabilities are tested for 40nm line 80nm pitch with the new bake plate hardware for below hp 3Xnm generation. For defectivity, the combination of Coater/Developer defect reduction hardware with the novel immersion hood design will be tested. For CDU improvements, the enhanced Post Exposure Bake (PEB) plate hardware was verified versus performance of the previous technology plate. Additionally, after the PEB improvement, a remaining across wafer signature was reduced with an optimized develop process. The total CDU budget was analyzed and compared to previous results. Finally the optimized process was applied to a non top coat resist process. For defectivity improvements, the effectiveness of ASML's new immersion hood and TEL's defect reduction hardware were evaluated. The new immersion hood performance was optimal on very hydrophobic materials, which requires optimization of the track hardware and process. The high contact angle materials could be shown to be successfully processed by using TEL's Advanced Defect Reduction (ADR) for residues related to the high contact angle and optimized bevel cut strategy with new bevel rinse hardware. Finally all the optimized processes were combined to obtain defect counts on a highly hydrophobic resist well within manufacturing specifications.

This paper reports the extracted risk issues on practical EUV resist processes and discusses verifications of them. The risk issues were extracted with emphasis on critical dimension, defectivity and productivity for mass production EUV resist processes. The authors verified these risk factors by utilizing available empirical knowledge. The authors found that the micro loading effect of by-product in the resist development process was a key factor for CD uniformity. Also discovered, was that high surface energy differences on the patterned wafers were a key factor for defectivity. As a result, application of scan-dynamic development and dynamic scan rinse to EUV processes on a mass production level will contribute greatly to CD and defect control as well as productivity.

As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Al pha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work 1 , processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACT™12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track proce ssing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current proce ssing conditions. From analysis of these data, it’s shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV. Keywords: EUV, CD, Defectivity

After an analysis of the factors that causes critical dimension (CD) variation in the lithography process of the LLE (Litho-Litho-Etch) double-patterning technology that employs the freezing process, an optimum process for freezing the resist patterns to reduce the CD variation, which occurs after the 2 nd litho process, was achieved. By optimizing the track parameters of freezing process, CD variation is likely to be reduced not only in the 1 st resist pattern but also in the 2 nd resist pattern. The optimum conditions were adopted to form patterns of 40 nm resist lines and spaces in the evaluations conducted in this paper. The formation result showed improvement of 3 sigma of the within-wafer CD uniformity of both the 1 st resist pattern and the 2 nd resist pattern, by about 13% and 46% respectively. Keywords: Double-patterning, Litho-Litho-Etch, Freezing 1. INTRODUCTION With the conventional immersion lithography technologies, scale-down further than 45 nm is difficult to realize. As new scale-down methods, technologies such as immersion lithography using high refractive index fluid, double-patterning, and Extreme Ultra Violet lithography have been developed. Among them, double-patterning is the most promising technology for 32 nm node. Double-patterning uses the lithography process twice in one of the following two ways to form fine, dense circuit patterns: the LELE (Litho-Etch-Litho-Etch) process, in which the lithography and etching processes are repeated twice; the LLE (Litho-Litho-Etch) process, in which the lithography process is repeated twice before one etching process. The LLE process eliminates the etching process performed after the first lithography process in the LELE process, thereby reducing the Cost of Ownership. However, performing resist coating and exposure over the first resist pattern is accompanied by the risk of deviation from the original resist pattern dimensions. The freezing process is one of the candidates of LLE process to solve this issue. Specifically, the freezing process is performed on the resist pattern formed in the first lithography process to give it resistance against the second lithography process to reduce its effects. This paper analyzes, using latest lithography tools, resist pattern dimensional variation that occurs in the double-patterning process that uses the freezing process. The result show process performance (within-wafer CD uniformity) of 40 nm hp in the case of latest lithography tools and optimum processes of the freezing process.

As lithographic technology is moving from single pattern immersion processing for 45nm node to double patterning for the next generation and onward to EUV processing, TEL is committed to understanding the fundamentals and improving our technology to enable customers to meet roadmap expectations. With regards to immersion and double patterning technology, TEL has presented a wide variety of technologies to advance the processing capability of our customers. With regards to EUV technology, we have previously presented work for simulation and modeling of an EUV resist system1 in order to further our understanding of the differences between resist performance from previous platforms and currently available EUV resists. As it's currently unknown which direction resist suppliers will take with regards to platform in order to surpass the current limitations in resolution, roughness and sensitivity trade off's, we need to consider the implications of such kinds of novel platforms to track processing capabilities. In this work, we evaluated two of the more promising materials, to determine processing sensitivities necessary for the development of new hardware and process applications. This paper details the initial study complete for understanding the track process parameters such as dissolution characteristics and the impact of film hydrophobicity. Fundamental processing knowledge from 193 and 248nm technology is applied to understand where processing deviates from known sensitivities and will require more development efforts.

Critical dimension uniformity (CDU) has both across field and across wafer components. CD error generated by across wafer etching non-uniformity and other process variations can have a significant impact on CDU. To correct these across wafer systematic variations, compensation by exposure dose and/or post exposure bake (PEB) temperature have been proposed. These compensation strategies often focus on a specific structure without evaluating how process compensation impacts the CDU of all structures to be printed in a given design. In one previous study limited to a single resist and minimal coater/developer and scanner variations, the authors evaluated the relative merits of across wafer dose and PEB temperature compensation on the process induced CD bias and CDU. For the process studied, it was found that using PEB temperature to control CD across wafer was preferable to using dose compensation. In another previous study, the impact of resist design was explored to understand how resist design, as well as coater/developer and scanner processing, impact process induced bias (PIB). The previous PIB studies were limited to a single illumination case and explore the effect of PIB on only L/S structures. It is the goal of this work to understand additionally how illumination design and mask design, as well as resist design and coater/developer and scanner processing, impact process induced bias (PIB)/OPC integrity.

Through collaborative efforts ASML and TEL are continuously improving the process performance for the LITHIUS Pro -i/ TWINSCAN XT:1900Gi litho cluster. In previous work from this collaboration, TEL and ASML have investigated the CDU and defectivity performance for the 45nm node with high through put processing. CDU performance for both memory and logic illumination conditions were shown to be on target for ITRS roadmap specifications. Additionally, it was shown that the current defect metrology is able to measure the required defect size of 30nm with a 90% capture rate. For the target through put of 180wph, no added impact to defectivity was seen from the multi-module processing on the LITHIUS Pro -i , using a topcoat resist process. For increased productivity, a new bevel cut strategy was investigated and shown to have no adverse impact while increasing the usable wafer surface. However, with the necessity of double patterning for at least the next technology node, more stringent requirements are necessary to prevent, in the worst case, doubling of the critical dimension variation and defectivity. In this work, improvements in process performance with regards to critical dimension uniformity and defectivity are investigated to increase the customer's productivity and yield for whichever double patterning scheme is utilized. Specifically, TEL has designed, evaluated and proven the capability of the latest technology hardware for post exposure bake and defect reduction. For the new post exposure bake hardware, process capability data was collected for 40nm CD targets. For defectivity reduction, a novel concept in rinse technology and processing was investigated on hydrophobic non top coat resists processes. Additionally, improvements to reduce micro bridging were evaluated. Finally bevel rinse hardware to prevent contamination of the immersion scanner was tested.

For lithography technology to support the scaling down of semiconductor devices, 193-nm immersion exposure processing is being introduced to mass-production at a rapid pace. At the same time, there are still many unclear areas and many concerns to be addressed with regards to defects in 193-nm immersion lithography. To make 193-nm immersion lithography technology practical for mass production, it is essential that the defect problems be solved. Importance must be attached to understanding the conditions that give rise to defects and their transference in the steps between lithography and etching processes. It is apparent that double patterning (DP) will be the mainstream technology below 40nm node. It can be assumed that the risk of the defect generation will rise, because the number of the litho processing steps will be increased in DP. Especially, in the case of Litho-Etch-Litho-Etch (LELE) process, the concept of defect transfer becomes more important because etch processing is placed between each litho processing step. In this paper, we use 193-nm immersion lithography processing to examine the defect transference from lithography through the etching process for a representative 45nm metal layer substrate stack for device manufacturing. It will be shown which types of defects transfer from litho to etch and become killer defects.

Printing random Contact Holes (C/H) is one of the most difficult tasks in current low-k1 lithography. Different approaches have been proposed and demonstrated successfully. One approach is the use of extensive Resolution Enhancement Technique such as sub-resolution assisting features, focus drilling and interference mapping lithography in combination with strong off-axis illumination. These techniques often lead to enhanced complexity at the OPC and mask making side. In order to keep the complexity low, soft illumination modes have been proposed like Soft-Annular (bull'seye) and Soft-Quasar type illumination [1]. It has been shown that the minimum k1 for the latter route is k1=0.41 using experimental results up to 0.93 NA. In this paper we demonstrate that the latter route can be extended to 45nm C/H at a minimum pitch of 120nm when using 1.35 NA. In order to achieve this we additionally applied a CD sizing technique to create the very small C/H.

In order to prepare for the next generation technology manufacturing, ASML and TEL are investigating the process manufacturability performance of the CLEAN TRACK TM LITHIUS Pro TM - i / TWINSCAN TM XT:1900Gi lithocluster at the 45nm node. Previous work from this collaboration showed the feasibility of 45nm processing using the LITHIUS TM i +/TWINSCAN XT:1700i. 1 In this work, process performance with regards to critical dimension uniformity and defectivity are investigated to determine the robustness for manufacturing of the litho cluster. Specifically, at the spinner and PEB plate configuration necessary for the high volume manufacturing requirement of 180 wafers per hour, process data is evaluated to confirm the multi-module flows can achieve the required process performance. Additionally, an improvement in the edge cut strategy necessary to maximize the usable wafer surface without negative impact to defectivity is investigated.

In order to prepare for the next generation technology manufacturing, ASML and TEL are working together to investigate the process performance of the LITHIUSi+/ TWINSCAN XT:1700i lithocluster through decreasing critical dimension patterning. In this evaluation, process performance with regards to critical dimension uniformity and defectivity are compared at different critical dimensions in order to determine areas of concentration for equipment and process development. Specifically, design of experiments were run using immersion rinse processing at 60nm hp and 45nm hp. Defects were classified to generate a pareto for each technology node to see if there is any change in the defect types as critical dimensions are shrinking. Similarly, critical dimension uniformity was compared through technology nodes to see if any budget contributions have increased sensitivities to the smaller patterning features. Preliminary gauge studies were performed for the 45nm hp evaluation, as metrology at this design rule is not yet fully proven. More work is necessary to obtain complete understanding of metrology capabilities as this is crucial to discern precise knowledge of processing results. While preliminary results show no adverse impact moving forward, this work is a first screening of 45nm immersion processing and more work is needed to fully characterize and optimize the process to enable robust manufacturing at 45nm hp.

The electrical resistivity, the magnetic susceptibility and the unit-cell dimensions of BaVS 3 with the BaNiO 3 -type structure were measured between 4 K and 300 K. A crystallographic transition from hexagonal to orthorhombic (D 6h 4 to D 2 5 ), that makes the –V 4+ –V 4+ – chains slightly zigzagging, was found at 258 K. The resistivity measured on sintered samples, however, increased very sharply below about 70 K. This sharp increase has been supposed to be due to an antiferromagnetic ordering which was suggested by a sharp peak at 74 K of the susceptibility vs temperature curve and was confirmed by the Mossbauer effect of a sample containing 57 Fe-impurity.