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A radiation-hardened-by-design (RHBD) technique is described for reducing errors due to single-event effects at the floating input nodes of a switched-capacitor comparator. The technique is shown to significantly outperform the alternative 'brute force' design choice of increasing capacitor size. Index Terms--Comparator, radiation-hardened-by-design, RHBD, single-event, switched-capacitor circuits.

A voltage-controlled-oscillator (VCO) circuit has been designed for radiation-hardened-by-design (RHBD) single-event transient (SET) mitigation. The RHBD technique, which can be readily implemented in mixed-signal phase-locked loops and delay-locked loops, is shown to substantially improve the single-event performance of the VCO while decreasing the rms phase jitter due to power supply noise. Additionally, using the probabilistic analysis technique presented, the RHBD VCO shows a maximally improved SET response over that of the conventional VCO, decreasing the output phase displacement to below the nominal phase jitter. Index Terms--Delay-locked loops, phase-locked loops, radiation effects, radiation hardening, single-event transients, voltage-controlled oscillators.

A built-in self-test technique for testing digital logic circuits for single-events has been developed. The BIST technique can be used for single-event testing in any conventional laboratory to evaluate the circuit level response to SEs. Experimental and simulation results for multiple technology nodes show the feasibility of this approach to test circuits, with the added advantages of reduced testing time and cost. Index Terms--Current-starved inverters, digital circuits, random number generator, single-events, single-event transients.

Mixed mode simulations and heavy-ion experiments indicate the presence of multi-node charge collection in advanced technologies. For logic circuits, such charge collection may result in concatenation of transients, extending the width of SETs. Mixed-mode simulations of a 4-bit adder circuit indicate that the increase in SET pulse width due to two-node charge collection can be as high as 75%. An analytical model for the increase in the SET width is developed showing the increase in SET width is proportional to the width of the individual transients, the relative delay between charge collection nodes, and the circuit topology. Index Terms--Charge sharing, multi-node charge collection, pulse width, single event, single-event transient (SET).

Frequency domain analysis is shown to be useful for quantifying the single-event vulnerability of a mixed-signal circuit. Frequency domain single-event analysis is demonstrated for different pipelined analog-to-digital converter topologies. Design tradeoffs of comparator redundancy are evaluated using a signal-to-noise ratio metric. Index Terms--Analog-to-digital converter (ADC), discrete Fourier transforms, pipeline, single-event.

The floating amplifier inputs in switched-capacitor differential circuits are identified as extremely vulnerable to single events. A radiation hardened by design mitigation technique is presented. The vulnerability of the floating inputs is improved by an order of magnitude with negligible penalties in area, power, speed and noise performance. Index Terms--Analog, mixed signal, radiation hardened by design (RHBD), single-event effect, switched capacitor.

Mixed mode TCAD simulations are used to show the effects of guard bands and high density well contacts in maintaining the well potential after a single event strike and thus reduce the width of long transients in a 130-nm CMOS process. Experimental verification of the effectiveness in mitigating long transients was achieved by measuring the distribution of SET pulse widths produced by heavy ions for circuits with isolated contacts and for circuits with guard bands combined with larger contacts in a 130-nm process using an autonomous characterization technique. Heavy-ion test results indicate that controlling the well potential by using guard bands, along with high density well contacts, helps eliminate > 70 % of SETs longer than 1 ns. Index Terms--CMOS, guard band, parasitic bipolar, pulse width, single event transient (SET), single event upset (SEU), soft error, well contact.

Single-event transients (SETs) affecting a single side of a differential data path have been shown to cause signal degradation and data loss. A radiation hardened by design (RHBD) transistor layout technique is demonstrated that promotes charge collection on both sides of the differential data path. The induced common-mode error voltage is suppressed by the differential circuit, significantly reducing the SET amplitude. Index Terms--Differential circuits, layout mitigation technique, radiation hardening by design (RHBD), single-event transient (SET).

Radiation effects on four common DC linear voltage regulators are investigated. Increasing total dose is shown to degrade converter regulation by degrading the loop gain and phase response. Regulator single event transient (SET) response is characterized, and a mitigation technique is proposed. Shunt regulator topologies are found to be superior to series regulator topologies in terms of radiation tolerance. Index Terms--Frequency response, linear voltage regulator, single event transient (SET), total ionizing dose.

Negative bias temperature instability has been experimentally demonstrated to increase the cross-section of the single event response for 40 nm flip-flops. Analysis on the underlying mechanisms, including threshold voltage shift, is presented. [ABSTRACT FROM AUTHOR]

Presents information as it relates to the fabrication of an integrated noise source (INS) in a standard 1.2 m digital CMOS technology. How wideband noise is generated; Details on the INS; Inclusions in the potential applications of the INS.