Search

Retention characteristics of 3D NAND Flash cells are investigated at various temperatures ( ${T}$ ) depending on the degree of program and erase. The $\Delta {V}_{\text {th}}$ for each condition is compared to understand the degradation of the retention characteristics attributable to vertical loss and/or lateral diffusion. In addition, the relationship between Program/Erase (PE) window (PGM ${V}_{\text {th}}$ – Erase ${V}_{\text {th}}$ ) and $\Delta {V}_{\text {th}}$ are analyzed. In the case when PGM ${V}_{\text {th}}$ is the same, the $\Delta {V}_{\text {th}}$ decreases as the PE window decreases. At temperatures below 150 °C, $\Delta {V}_{\text {th}}$ and PE window show linear relationship, and as PE window decreases, $\Delta {V}_{\text {th}}$ also decreases to 0. On the other hand, at 250 °C, $\Delta {V}_{\text {th}}$ has a non-zero value even if PE window decreases to 0, thus has a non-linear relationship. The measurement results show that the lateral diffusion has a great influence on the short-term retention of 3D NAND flash cells.

In this work, a novel synaptic array architecture enabling forward propagation (FP) and backward propagation (BP) in the NAND flash memory is proposed for the first time for on-chip learning. In the proposed synaptic architecture, positive synaptic weight and negative synaptic weight are separated in different arrays to enable weights to be transposed correctly. In addition, source-lines (SLs) are separated, which is different from the conventional NAND flash memory, to enable both the FP and BP in the NAND flash memory. By applying input and error input to bitlines (BLs) and string-select lines (SSLs) in NAND cell array, respectively, accurate vector–matrix multiplication is successfully carried out in both FP and BP eliminating the effect of pass cells. At a read voltage of 2 V, the inference accuracy of 95.58% which is comparable to that of 95.81% obtained with perfect linear device is achieved. The proposed on-chip learning system is much more robust to weight variation compared to the off-chip learning system. Finally, superiority of the proposed on-chip learning architecture is verified by circuit simulation of a neural network.

Dynamic random-access memory (DRAM) peripheral nMOSFETs with various channel length and channel doping concentration are analyzed at liquid nitrogen temperature (LNT). Important device parameters in circuit designs such as subthreshold mismatch, subthreshold swing (SS), transconductance, and drain-induced barrier lowering (DIBL) are analyzed at temperatures ranging from room temperature to LNT. In devices with relatively low channel doping, exacerbation of threshold mismatch at cryogenic temperatures is alleviated. Devices with lower doping exhibit better SS and transconductance characteristics. DIBL improved in short-channel devices at cryogenic temperatures, and the degradation of the DIBL with low doping is relatively small.

A hardware-based neural network that enables on-chip training using a thin-film transistor-type AND flash memory array architecture is designed. The synaptic device constituting the array is characterized by a doped $p$ -type body, a gate insulator stack composed of SiO2/Si3N4/Al2O3, and a partially curved poly-Si channel. The body reduces the circuit burden on the high voltage driver required for both the source and drain lines when changing the synaptic weights. The high- $\kappa $ material included in the gate insulator stack helps to lower the operating voltage of the device. As the device scales down, the structural characteristics of the device have the potential to increase the efficiency of the memory operation and the immunity to the voltage drop effect that occurs in the bit-lines of the array. In an AND array architecture using fabricated synaptic devices, a pulse scheme for selective memory operation is proposed and verified experimentally. Due to the direct feedback alignment (DFA) algorithm, which does not need to have the same synaptic weight in the forward path and backward path, the AND array architecture can be utilized in designing an efficient on-chip training neural network. Pulse schemes suitable for the proposed AND array architecture are also devised to implement the DFA algorithm in neural networks. In a system-level simulation, a recognition accuracy of up to 97.01% is obtained in the MNIST pattern learning task based on the proposed pulse scheme and computing architecture.

A novel design method using unsigned input is proposed for a high-density and parallel synaptic string architecture capable of bit-wise operation and bit-counting utilizing NAND flash memory. Though the NAND flash memory has a cell string structure, unsigned binary input enables analogue and parallel bit-counting in NAND flash memory, while achieving high accuracy comparable to that of signed input. Adopting unsigned input allows using current sense amplifier as neuron circuit, which reduces burden of peripheral circuits. In addition, the operation scheme for convolution layers is proposed for parallel convolution operation utilizing NAND flash memory. We show that sufficiently low device variation of 7.2 % obtained by applying 1 erase or program pulse achieves accuracy of 98.12 % and 87.12 % for MNIST and CIFAR 10 patterns, respectively.

We propose a novel synaptic architecture based on a NAND flash memory for highly robust and high-density quantized neural networks (QNN) with 4-bit weight and binary neuron activation, for the first time. The proposed synaptic architecture is fully compatible with the conventional NAND flash memory architecture by adopting a differential sensing scheme and a binary neuron activation of (1, 0). A binary neuron enables using a 1-bit sense amplifier, which significantly reduces the burden of peripheral circuits and power consumption and enables bitwise communication between the layers of neural networks. Operating NAND cells in the saturation region eliminates the effect of metal wire resistance and serial resistance of the NAND cells. With a read-verify-write (RVW) scheme, low-variance conductance distribution is demonstrated for 8 levels. Vector-matrix multiplication (VMM) of a 4-bit weight and binary activation can be accomplished by only one input pulse, eliminating the need of a multiplier and an additional logic operation. In addition, quantization training can minimize the degradation of the inference accuracy compared to post-training quantization. Finally, the low-variance conductance distribution of the NAND cells achieves a higher inference accuracy compared to that of resistive random access memory (RRAM) devices by 2~7 % and 0.04~0.23 % for CIFAR 10 and MNIST datasets, respectively.

With ability to process data in an energy-efficient way, neuromorphic computing is suggested to overcome the issues of a traditional von Neumann computing system. Neuromorphic computing is composed of two crucial features of neurons and synapses, in which neurons integrate all the charges while synapses retain these charges. In this paper, we fabricate and analyze devices for mimicking neurons and synapses in a single Si-based metal-oxide-semiconductor field-effect transistor (MOSFET) structure. We fabricate and analyze Al2O3/Si3N4 (A/N) and Al2O3/HfO2/Si3N4/SiO2 (A/H/N/O) devices to suggest that an A/N device could be used as a neuron device due to its fast charge emission characteristics, while the A/H/N/O device could be used as a synaptic device as added tunneling SiO2 causes the device to retain its charges for a long-period of time. We suggest the possibility of fabricating both neurons and synapses by adopting different gate insulator stack structures in MOSFETs.

A novel synaptic architecture based on NAND cell strings is proposed as a high-density synapse capable of XNOR operation for binary neural networks (BNNs) for the first time. By changing the threshold voltage of NAND flash cells and input voltages in complementary fashion, the XNOR operation is successfully demonstrated. The large on/off current ratio (~7×105) of NAND flash cells can implement high-density and highly-reliable BNNs without error correction codes. It is shown that without conventional ISPP scheme, only 1 erase or program pulse can achieve sufficiently low bit-error rate. Finally, the estimated synapse area of VNAND memory with 128 stacks is ~100 times that of 2T2R synapse in RRAMs.

We have investigated the temperature dependence of electrical conductivity and thermoelectric power (TEP) at 1.7 K T 2+ chelate. We observed intrinsic metallic temperature dependence of resistivity from room temperature to 68 K with a broad minimum [ ρ (68 K)/ ρ (300 K) ∼0.75], which has not been observed previously in similar organo metallic complexes. There occurs an unusual metal-insulator transition at T ∼68 K and the resisitivity increases upon cooling below 68 K. However, the low temperature resistivity becomes finite (instead of going to infinity), [ρ(1.7 K)/ ρ (300 K) ∼0.98] indicating that a quantum mechanical tunneling conduction is dominant at this low temperature. It is remarkable that the resistivity at 1.7 K is as small as that of room temperature. Such unusual temperature dependence of conductivity could be understood as thermally assisted hopping conduction between metallic islands. However, the observed intrinsic metallic temperature dependence of resistivity implies that such hopping conduction barrier is not important at high temperature ( T > 68 K). The intrinsic metallic characteristics are confirmed by the quasi-linear temperature dependence of TEP for the whole measured temperature range (1.7 K T T

In this paper we report on the thermopower and electrical conductivities of ${\mathrm{Ti}}_{4}{\mathrm{AlN}}_{2.9}$ and ${\mathrm{Ti}}_{3}{\mathrm{Al}}_{1.1}{\mathrm{C}}_{1.8}$ in the 300--850 K temperature range. We also measured the room temperature Hall effect in ${\mathrm{Ti}}_{3}{\mathrm{SiC}}_{2},$ ${\mathrm{Ti}}_{4}{\mathrm{AlN}}_{2.9},$ and ${\mathrm{Ti}}_{3}{\mathrm{Al}}_{1.1}{\mathrm{C}}_{1.8}.$ Based on these results we conclude that holes are the majority carriers at room temperature in ${\mathrm{Ti}}_{3}{\mathrm{Al}}_{1.1}{\mathrm{C}}_{1.8}$ and ${\mathrm{Ti}}_{4}{\mathrm{AlN}}_{2.9}.$ At higher temperatures free electrons contribute to the transport properties. ${\mathrm{Ti}}_{3}{\mathrm{SiC}}_{2}$ is a mixed conductor wherein the concentrations and mobilities of the free electrons are, respectively, equal to those of the holes over an extended temperature range. The high conductivity of ${\mathrm{Ti}}_{3}{\mathrm{SiC}}_{2}$ is due to the presence of a large concentration of charge carriers. The lower conductivity of ${\mathrm{Ti}}_{3}{\mathrm{Al}}_{1.1}{\mathrm{C}}_{1.8}$ is due to a dearth of charge carriers. The even lower conductivity of ${\mathrm{Ti}}_{4}{\mathrm{AlN}}_{2.9}$ is attributed to a reduced mobility, most probably due to vacancy scattering of the charge carriers.

Our Middle-1X nm MLC NAND (M1X) flash cell is intensively characterized with respect to reliability and manufacturability. For the first time, the novel active air-gap technology is applied to alleviate the drop of channel boosting potential of program inhibition mode, BL-BL interference is reduced to our 2y nm node level by this novel integration technology. Furthermore, it also relaxes the effect of process variation like EFH (Effective Field oxide Height) on cell Vt distribution. Better endurance and retention characteristics can be obtained by p+ doped poly gate. By optimization of active air-gap profile and poly doping level, M1X nm MLC NAND flash memory has been successfully implemented with superior manufacturability and acceptable reliability.

Magnetoresistance (MR) and magnetothermoelectric power (MTEP) of iodine-doped single-walled carbon nanotubes (I@SWNT) under magnetic fields up to 14 T are investigated from room temperature (300 K) down to 1.6 K. Our results on resistivity and thermoelectricpower (TEP) in a zero magnetic field are similar to those reported by Grigorian et al. [Phys. Rev. Lett. 80, 5560 (1998)] The positive sign of the TEP values indicates that the majority of the carriers in the I@SWNT are holes. The broad enhancement of TEP at temperatures of 30\char21{}200 K shows quasilinear temperature dependence and is consistent with sharply varying density of states near the Fermi level with additional contribution from the spin-orbit scattering in the normal metallic characteristics of the I@SWNT. For $Tl7\text{ }\text{K}$, MR is negative and it decreases with ${H}^{2}$ followed by the ${H}^{1/2}$ dependence at around $H=2\text{ }\text{T}$ which is characteristic for the weak localization. In the range $7\text{ }\text{K}lTl70\text{ }\text{K}$, MR is positive at low magnetic field and becomes negative at higher magnetic field. The negative MR in the high magnetic fields decreases linearly. At $T\ensuremath{\ge}\ensuremath{\sim}100\text{ }\text{K}$, MR is positive up to 14 T, which could be the result of spin-orbit scattering in the I@SWNT. The MTEP decreases under magnetic field at $Tl90\text{ }\text{K}$. The reduction in MTEP is originated from the delocalization of electron wave functions under the magnetic field. At $Tg90\text{ }\text{K}$, the thermal fluctuation dominates the effect of magnetic fields resulting the MTEP to be the same as the zero magnetic field TEP.

In this paper we report on the electronic and magnetotransport properties of two Ti-based ternaries, ${\mathrm{Ti}}_{3}{\mathrm{AlC}}_{2}$ and ${\mathrm{Ti}}_{4}{\mathrm{AlN}}_{3}.$ In order to determine the effective carrier concentrations and their mobilities, the Hall effect, electrical conductivity, thermoelectric power, magnetic susceptibility, and magnetoresistance were measured as a function of temperature between 4 and 300 K and at magnetic fields up to 9 T. For ${\mathrm{Ti}}_{3}{\mathrm{AlC}}_{2},$ the Hall voltage is a linear function of magnetic field at all temperatures. At the lowest temperatures, the Hall coefficient is small but positive; above 100 K it is negative and drops more or less linearly with temperature. The magnetoresistance of ${\mathrm{Ti}}_{3}{\mathrm{AlC}}_{2}$ is dominated by a positive quadratic field dependence. The magnetic susceptibility is nearly constant but displays a weak maximum around the temperature at which the Hall effect changes sign (\ensuremath{\approx}100 K). In contrast, the Seebeck coefficient remains positive up to 800 K, with a maximum at 700 K. The results were analyzed within a two-band framework assuming a temperature-independent charge-carrier density and a hole mobility that is slightly smaller than the electron mobility. The model quantitatively accounts for our observations. The resistivity, magnetoresistance, and Hall coefficient of ${\mathrm{Ti}}_{4}{\mathrm{AlN}}_{3},$ on the other hand, were successfully described within the single-band model, with holes as the dominant charge carriers. This was supported by measurements of the Seebeck coefficient, which is positive and peaks at \ensuremath{\approx}300 K. The magnetic susceptibility of ${\mathrm{Ti}}_{4}{\mathrm{AlN}}_{3}$ is also quite temperature independent.