599 results on '"Horiguchi, N."'
Search Results
2. Dual Operation of Gate-All-Around Silicon Nanowires at Cryogenic Temperatures: FET and Quantum Dot
3. Impact of work function metal stacks on the performance and reliability of multi-Vth RMG CMOS technology
4. Characterization of DC performance and low-frequency noise of an array of nMOS Forksheets from 300 K to 4 K
5. CMOS Scaling by Nanosheet Device Architectures and Backside Engineering
6. Towards Improved Nanosheet-Based Complementary Field Effect Transistor (CFET) Performance Down to 42nm Contacted Gate Pitch
7. Forksheet Field-Effect Transistors for Area Scaling and Gate-Drain Capacitance Reduction in Nanosheet-based CMOS Technologies
8. Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis
9. Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application
10. 3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling
11. Ultimate Layer Stacking Technology for High Density Sequential 3D Integration
12. Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
13. Dry etch challenges for patterning middle-of-line (MOL) contact trench in monolithic CFET (complementary FET)
14. Integration of a Stacked Contact MOL for Monolithic CFET
15. Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions
16. Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET
17. Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning
18. Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET
19. Reliability challenges in Forksheet Devices: (Invited Paper)
20. Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures
21. Insights into Scaled Logic Devices Connected from Both Wafer Sides
22. Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells
23. Low thermal budget PBTI and NBTI reliability solutions for multi-Vth CMOS RMG stacks based on atomic oxygen and hydrogen treatments
24. Low temperature source/drain epitaxy and functional silicides: essentials for ultimate contact scaling
25. FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral Circuits
26. Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
27. Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling
28. FinFETs and Their Futures
29. Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
30. High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories
31. Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO
32. Ni(Pt) silicide with improved thermal stability for application in DRAM periphery and replacement metal gate devices
33. Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets
34. Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery
35. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks
36. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
37. Inspection and metrology challenges for 3 nm node devices and beyond
38. Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices
39. Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
40. Low-temperature atomic and molecular hydrogen anneals for enhanced chemical $\mathbf{SiO}_{2}$ IL quality in low thermal budget RMG stacks
41. Buried Power Rail Metal exploration towards the 1 nm Node
42. Properties of ALD TaxNy films as a barrier to aluminum in work function metal stacks.
43. Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper
44. Challenges in using optical lithography for the building of a 22 nm node 6T-SRAM cell
45. Electrical demonstration of thermally stable Ni silicides on Si 1−xC x epitaxial layers
46. Reliability of Barrierless PVD Mo
47. Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations
48. Combining TCAD and advanced metrology techniques to support device integration towards N3
49. Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond
50. Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.