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Instability threshold voltage (VT) with retention loss of read-after-write is a critical issue with fundamental physics for ferroelectric field effect transistors (FeFETs) scaling down under high-speed operation. The mechanisms including charge trapping and depolarization field (Edep) are discovered and related to surface potential and coercive field (EC). The trapped charge can be effectively detrapped by opposite polarity stimulation and validated by technology computer-aided design modeling. In addition, the Edep is revealed to be serious with ferroelectric HfZrO2 (FE-HZO) thin-down due to the unstable low-VT state at a gate voltage (VG) of 0 V. The tunable base voltage (Vbase) compensates the Edep-based polarization degradation. A stable low-VT read-after-write for a 5-nm-thick HZO FeFET is experimentally demonstrated by the opposite polarity detrapping scheme hybrid with a Vbase optimization simultaneously for a wide range of delay times from 10−7 to 102 s. This result provides the feasibility for scaling down FeFETs for nonvolatile memory applications in the future. [ABSTRACT FROM AUTHOR]

HfO2-based ferroelectric (FE–HfO2) is a promising material for low-power and high-capacity memory technology. Since thinner ferroelectric films are required for low voltage operation, the impact of film thickness on the switching kinetics of FE–HfO2 needs to be studied in detail. In this paper, metal/ferroelectric/metal capacitors are fabricated with several thicknesses of HfZrO2 (HZO) films and characterized to study the switching kinetics based on the nucleation limited switching (NLS) model. Thinner HZO capacitors show slower polarization switching and asymmetry in program and erase operation, although low-frequency polarization charge density is nearly the same for all thicknesses. Slow switching is due to the large variability of the activation field of FE domains and grain boundaries among small FE grains. The asymmetry is caused by the asymmetric interface property at the top and bottom interfaces. High-resolution TEM and electron diffraction mapping methods provide physical evidence for the above discussions. [ABSTRACT FROM AUTHOR]

In this article, we propose an energy-efficient monolithic 3-D (M3D) three-tier SRAM cell with back-end-of-the-line (BEOL) back-gated (BG) MoS2 FETs. The impacts of wire routing resistance and capacitance, gate topology of MoS2 FETs, and the layout optimization of multitier 6T SRAM cells have been comprehensively analyzed for SoC scaling through system-technology co-optimization. SRAM plays an integral role in the performance of SoCs, and the performance can be improved by SRAM on logic integration. Compared with one-tier BG SRAM cell design, the proposed monolithic three-tier BG SRAM cell releases the impact of metal line resistance and shows a 44.3% reduction in cell area, 28.4% improvement in read access time, 21.3% improvement in dynamic energy, and 43.6% improvement in energy-delay product. The energy- and area-efficient three-tier BG SRAM cell enables intelligent functionalities for the area- and energy-constrained edge computing devices. [ABSTRACT FROM AUTHOR]