171 results on '"Hu, Vita Pi-Ho"'
Search Results
2. Innovative Recovery Strategy for MFIS-FeFETs at Optimal Timing With Robust Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02%), and Self-Tracking Circuit Design
3. Energy-Efficient SRAM with Emerging Technologies
4. Improved Scalability of Negative Capacitance Junctionless Transistors With Underlap Design
5. Improved Radiation Hardness for Nanosheet FETs with Partial Bottom Dielectric Isolation
6. Analysis of Monolithic 3D SRAM with Back-End-of-Line-compatible Transistors
7. Stability and Performance Optimization of 6T SRAM Cell at Cryogenic Temperature
8. Linearity Analysis of FeFET Synaptic Devices considering Random Phase Distributions
9. Variation-Tolerant Ferroelectric FET-based Ternary Content-Addressable Memories (TCAM) Cell for Meta-learning Application
10. Mechanisms of instability retention for ferroelectric field effect transistors with HfZrO2 gate stack scaling down
11. Energy-and Area-Efficient 8T SRAM Cell with FEOL CFETs and BEOL-Compatible Transistors
12. Introducing the Editorial Board [The Editor’s Desk]
13. On the thickness dependence of the polarization switching kinetics in HfO2-based ferroelectric
14. Sensitivity Analysis of Ferroelectric Junctionless Transistors for Non-volatile Memory Applications
15. Variation-Tolerant Recall Operation for Nonvolatile SRAM Integrated with Ferroelectric Capacitor
16. Mechanisms of instability retention for ferroelectric field effect transistors with HfZrO2 gate stack scaling down.
17. 2D Materials‐Based Static Random‐Access Memory.
18. Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model
19. High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing
20. Optimization of Junctionless Ferroelectric Field-Effect Transistors for Non-Volatile Memory Applications
21. Static Noise Margin Analysis for Cryo-CMOS SRAM Cell
22. Sensitivity Analysis and Design of Negative-Capacitance Junctionless Transistor for High-Performance Applications
23. On the thickness dependence of the polarization switching kinetics in HfO2-based ferroelectric.
24. Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node
25. Introducing the Editorial Board
26. Energy-Efficient Monolithic 3-D SRAM Cell With BEOL MoS2 FETs for SoC Scaling
27. Improved Energy Efficiency for Ferroelectric FET Non-Volatile Memory using Split-Gate Design
28. Subthreshold Behavior of Ferroelectric Junctionless Transistor
29. Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)
30. Negative Capacitance Junctionless Device With Mid-Gap Work Function for Low Power Applications
31. Comparative Analysis of Negative Capacitance Junctionless and Inversion Mode Transistors for Low Power Applications
32. Evaluation of Analog Circuit Performance for Ferroelectric SOI MOSFETs considering Interface Trap Charges and Gate Length Variations
33. Reduced RTN Amplitude and Single Trap induced Variation for Ferroelectric FinFET by Substrate Doping Optimization
34. Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications
35. Improved Read Stability and Writability of Negative Capacitance FinFET SRAM Cell for Subthreshold Operation
36. Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET
37. Impact of Work Function Variation, Line-Edge Roughness, and Ferroelectric Properties Variation on Negative Capacitance FETs
38. Energy-Efficient Monolithic 3-D SRAM Cell With BEOL MoS2 FETs for SoC Scaling.
39. Analysis of heterojunction GaAs1−xSbx/In1−yGayAs tunnel FETs considering line tunneling
40. Device design of vertical nanowire III-V heterojunction TFETs for performance enhancement
41. Optimization of III–V heterojunction tunnel FET with non-uniform channel thickness for performance enhancement and ambipolar leakage suppression
42. Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation
43. Device Designs of III-V Tunnel FETs for Performance Enhancements through Line Tunneling
44. Analysis of switching characteristics for negative capacitance ultra-thin-body germanium-on-insulator MOSFETs
45. Negative capacitance enables FinFET and FDSOI scaling to 2 nm node
46. Reliability-Tolerant Design for Ultra-Thin-Body GeOI 6T SRAM Cell and Sense Amplifier
47. Analysis of subthreshold swing and internal voltage amplification for hysteresis-free negative capacitance FinFETs
48. Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs
49. Corner spacer design for performance optimization of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap
50. Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.