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A 5-13.5 Gbps multi-standard I/O link receiver is presented in this paper. An inductor-free CTLE, whose gain and bandwidth are highly adjustable, is achieved by using the second-order negative capacitance circuit. A high jitter tolerance clock and data recovery (HJTOL-CDR) is proposed for Spread Spectrum Clock applications. In this work, the JTOL is improved by two ways: first, a partial-noise-shaping-based digital loop filter (PNS-DLF) is implemented to reduce the output jitter caused by the truncation error in the integral path; second, the proposed CDR logic is fully custom designed to operate at a quarter-rate clock of 5 GHz. Moreover, the CDR bandwidth can be tuned to satisfy various data rates and jitter masks. Post-layout simulation shows that the proposed CTLE can provide wide gain tuning range, the boost gain at 10 GHz is beyond 29 dB and the proposed CDR can tolerate up to 31-kppm frequency offset. The proposed receiver is fabricated in 40-nm CMOS with an active area of 0.06 mm2 and 65 mW power consumption at 20 Gbps from 1.2-V supply. Measurement results show that, when receiving the PRBS31 data at 10 Gbps with 5-kppm frequency offset across a channel with 14-dB loss, the JTOL is 0.39 UIpp at 10 MHz and can guarantee a 0.34 UIpp at high frequency, which proves that the proposed receiver can meet stringent standards such as PCIe 3.0/4.0, USB 3.2, DisplayPort 1.4.

In complex environment, the wireline voltage driver should be compatible with wide-terminal common-mode range, electrostatic discharge (ESD), and radiation interference. The most vulnerable devices in the conventional driver are the nMOS transistor and the silicon-controlled rectifier (SCR) against negative the ESD shock, total dose radiation, and single-event latch-up. In this paper, a reliable wireline driver circuit is proposed compatible with −7 ~ 12-V terminal common-mode voltage range. By adopting face-to-face diodes, pMOS/n-p-n hybrid driver, and Schottky diodes, the proposed driver circuit demonstrates significant protection level improvement for both ESD and radiation. Both the reference SCR-based driver and the proposed driver with the optimized circuit design and protection strategy are fabricated using a 0.6- $\mu \text{m}$ bipolar-CMOS-DMOS process. Due to a simpler circuit structure, the proposed output stage has about 10% less chip area. According to the measurement results, the human-body-model ESD level of 3 kV, total dose radiation level of 100 krad(Si), and single-event effect level of 75 MeV $\cdot $ cm2/mg are achieved in the proposed design to satisfy complex environment applications.