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In this study, we investigate the reverse conduction diode mode failure mechanism in p-GaN gate high electron mobility transistors (HEMTs) using TCAD simulations and emission microscopy (EMMI). First, we observe a significant increase in gate leakage current when ${V}_{\text {DS}}$ is swept to −15 V while ${V}_{\text {GS}} =0$ V, indicating gate breakdown occurring with sufficient negative bias. Second, TCAD simulations are conducted to gain further insight into the failure locations and mechanisms. The simulations reveal high electric fields in the Schottky junction close to the interface between the metal and the p-GaN. This finding suggests that the gate region is likely the location leading to increased gate current and breakdown during the reverse conducting operation of the p-GaN gate HEMT. Lastly, EMMI measurements are performed on a device exhibiting high gate leakage current during reverse conduction diode mode operation. The EMMI results show bright spots in the gate region, which align with the failure location identified by the TCAD simulations. These results emphasize the importance of optimizing the Schottky/p-GaN junction to enhance the robustness of the p-GaN gate HEMT under reverse conduction diode mode operation.

Incorporating inhibition dynamics for the first time, in this work, we successfully model the trapping and detrapping kinetics under positive and negative bias stress in 4H-SiC MOS-capacitors. The positive/negative gate bias stress is applied during extended measure stress measure (eMSM)-fast C–V measurements, demonstrating noticeable trapping/detrapping dynamics. Analytical expressions based on the inhibition mechanism are developed to successfully model the trapping/detrapping phenomenon and estimate the location of the trap, which is found to be 1 nm from the dielectric/SiC interface due to border/interface traps. The developed analytical model can provide valuable insights in understanding positive/negative bias instability in SiC technology.