Search

Abstract Magnons, bosonic quasiparticles carrying angular momentum, can flow through insulators for information transmission with minimal power dissipation. However, it remains challenging to develop a magnon-based logic due to the lack of efficient electrical manipulation of magnon transport. Here we show the electric excitation and control of multiferroic magnon modes in a spin-source/multiferroic/ferromagnet structure. We demonstrate that the ferroelectric polarization can electrically modulate the magnon-mediated spin-orbit torque by controlling the non-collinear antiferromagnetic structure in multiferroic bismuth ferrite thin films with coupled antiferromagnetic and ferroelectric orders. In this multiferroic magnon torque device, magnon information is encoded to ferromagnetic bits by the magnon-mediated spin torque. By manipulating the two coupled non-volatile state variables—ferroelectric polarization and magnetization—we further present reconfigurable logic operations in a single device. Our findings highlight the potential of multiferroics for controlling magnon information transport and offer a pathway towards room-temperature voltage-controlled, low-power, scalable magnonics for in-memory computing.

Abstract Magnetic skyrmions have great potential for developing novel spintronic devices. The electrical manipulation of skyrmions has mainly relied on current-induced spin-orbit torques. Recently, it was suggested that the skyrmions could be more efficiently manipulated by surface acoustic waves (SAWs), an elastic wave that can couple with magnetic moment via the magnetoelastic effect. Here, by designing on-chip piezoelectric transducers that produce propagating SAW pulses, we experimentally demonstrate the directional motion of Néel-type skyrmions in Ta/CoFeB/MgO/Ta multilayers. We find that the shear horizontal wave effectively drives the motion of skyrmions, whereas the elastic wave with longitudinal and shear vertical displacements (Rayleigh wave) cannot produce the motion of skyrmions. A longitudinal motion along the SAW propagation direction and a transverse motion due to topological charge are simultaneously observed and further confirmed by our micromagnetic simulations. This work demonstrates that acoustic waves could be another promising approach for manipulating skyrmions, which could offer new opportunities for ultra-low power skyrmionics.

Abstract In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

Abstract Medical imaging is an important tool for accurate medical diagnosis, while state-of-the-art image reconstruction algorithms raise critical challenges in massive data processing for high-speed and high-quality imaging. Here, we present a memristive image reconstructor (MIR) to greatly accelerate image reconstruction with discrete Fourier transformation (DFT) by computing-in-memory (CIM) with memristor arrays. A high-accuracy quasi-analogue mapping (QAM) method and generic complex matrix transfer (CMT) scheme was proposed to improve the mapping precision and transfer efficiency, respectively. High-fidelity magnetic resonance imaging (MRI) and computed tomography (CT) image reconstructions were demonstrated, achieving software-equivalent qualities and DICE scores after segmentation with nnU-Net algorithm. Remarkably, our MIR exhibited 153× and 79× improvements in energy efficiency and normalized image reconstruction speed, respectively, compared to graphics processing unit (GPU). This work demonstrates MIR as a promising high-fidelity image reconstruction platform for future medical diagnosis, and also largely extends the application of memristor-based CIM beyond artificial neural networks.

Eighteen sun-dried tea samples were selected from six major tea-producing regions in Yunnan Province, namely Xishuangbanna, Pu'er, Lincang, Baoshan, Dehong and Yuxi to use for this study. In this study, these samples' biochemical components such as moisture, water leachate, caffeine, tea polyphenols and free amino acids were tested and their sensory evaluations were conducted. The quality differences of sun-dried tea from different regions in Yunnan Province were investigated by means of index correlation analysis, principal component analysis, cluster analysis and quality appellation analysis, and high-quality production regions were screened. The results showed that the quality indicators of different regional sun-dried tea had differences and there were some correlations among the quality indicators. Among them, the water leachate content showed correlation with the content of tea polyphenol and leaf base (P

Analog resistive random-access memory (RRAM)-based computation-in-memory (CIM) technology is promising for constructing artificial intelligence (AI) with high energy efficiency and excellent scalability. However, the large overhead of analog-to-digital converters (ADCs) is a key limitation. In this work, we propose a novel LINKAGE architecture that eliminates PE-level ADCs and leverages an analog data transfer module to implement inter-array data processing. A blockwise dataflow is further proposed to accelerate convolutional neural networks (CNNs) to speed up compute-intensive layers and solve the unbalanced pipeline problem. To obtain accurate and reliable benchmark results, key component modules, such as straightforward link (SFL) modules and Tile-level ADCs, are designed in standard 28 nm CMOS technology. The evaluation shows that LINKAGE outperforms the conventional ADC/DAC-based architecture with a 2.07×∼11.22× improvement in throughput, 2.45×∼7.00× in energy efficiency, and 22%–51% reduction in the area overhead while maintaining accuracy. Our LINKAGE architecture can achieve 22.9∼24.4 TOPS/W energy efficiency (4b-IN/4b-W) and 1.82 ∼4.53 TOPS throughput with the blockwise method. This work demonstrates a new method for significantly improving the energy efficiency of CIM chips, which can be applied to general CNNs/FCNNs.

Sound localization is one of the many learning tasks accomplished by the brain based on the binaural signals of the ears. Here, Wu et al demonstrate in-situ learning of sound localization function using a memristor array, with dramatic improvements in energy efficiency.

Reservoir computing has demonstrated high-level performance, however efficient hardware implementations demand an architecture with minimum system complexity. The authors propose a rotating neuron-based architecture for physically implementing all-analog resource efficient reservoir computing system.

Mathematical morphology operations are widely used in image processing such as defect analysis in semiconductor manufacturing and medical image analysis. These data-intensive applications have high requirements during hardware implementation that are challenging for conventional hardware platforms such as central processing units (CPUs) and graphics processing units (GPUs). Computation-in-memory (CIM) provides a possible solution for highly efficient morphology operations. In this study, we demonstrate the application of morphology operation with a novel memristor-based auto-detection architecture and demonstrate non-neuromorphic computation on a multi-array-based memristor system. Pixel-by-pixel logic computations with low parallelism are converted to parallel operations using memristors. Moreover, hardware-implemented computer-integrated manufacturing was used to experimentally demonstrate typical defect detection tasks in integrated circuit (IC) manufacturing and medical image analysis. In addition, we developed a new implementation scheme employing a four-layer network to realize small-object detection with high parallelism. The system benchmark based on the hardware measurement results showed significant improvement in the energy efficiency by approximately 358 times and 32 times more than when a CPU and GPU were employed, respectively, exhibiting the advantage of the proposed memristor-based morphology operation.

Abstract Ratio-based encoding has recently been proposed for single-level resistive memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding single-bit information, which significantly reduces the bit error probability. Generalizing this concept for multi-level cells, we propose a ratio-based information encoding mechanism and demonstrate its advantages over the resistance-based encoding for designing multi-level memory systems. We derive a closed-form expression for the bit error probability of ratio-based and resistance-based encodings as a function of the number of levels of the memory cell, the variance of the distribution of the resistive states, and the ON/OFF ratio of the resistive device, from which we prove that for a multi-level memory system using resistance-based encoding with bit error probability x, its corresponding bit error probability using ratio-based encoding will be reduced to $$x^2$$ x 2 at the best case and $$x^{\sqrt{2}}$$ x 2 at the worst case. We experimentally validated these findings on multiple resistance-switching devices and show that, compared to the resistance-based encoding on the same resistive devices, our approach achieves up to 3 orders of magnitude lower bit error probability, or alternatively it could reduce the cell’s programming time and programming energy by up 5–10 $$\times$$ × , while achieving the same bit error probability.

Designing efficient neuromorphic systems for complex temporal tasks remains a challenge. Zhong et al. develop a parallel memristor-based reservoir computing system capable of tuning critical parameters, achieving classification accuracy of 99.6% in spoken-digit recognition and time-series prediction error of 0.046 in the Hénon map.

Here, the authors demonstrate an atomic threshold-switching field-effect transistor constructed by integrating a metal filamentary switch with a two-dimensional MoS2 channel, and obtain abrupt steepness in the turn-on characteristics and 4.5 mV/dec subthreshold swing over five decades.

The long-time retention issue of resistive random access memory (RRAM) brings a great challenge in the performance maintenance of large-scale RRAM-based computation-in-memory (CIM) systems. The periodic update is a feasible method to compensate for the accuracy loss caused by retention degradation, especially in demanding high-accuracy applications. In this paper, we propose a selective refresh strategy to reduce the updating cost by predicting the devices’ retention behavior. A convolutional neural network-based retention prediction framework is developed. The framework can determine whether an RRAM device has poor retention that needs to be updated according to its short-time relaxation behavior. By reprogramming these few selected devices, the method can recover the accuracy of the RRAM-based CIM system effectively. This work provides a valuable retention coping strategy with low time and energy costs and new insights for analyzing the physical connection between the relaxation and retention behavior of the RRAM device.

Designing energy efficient and high performance brain-machine interfaces with millions of recording electrodes for in-situ analysis remains a challenge. Here, the authors develop a memristor-based neural signal analysis system capable of filtering and identifying epilepsy-related brain activities with an accuracy of 93.46%.

Abstract Memory cells have always been an important element of information technology. With emerging technologies like big data and cloud computing, the scale and complexity of data storage has reached an unprecedented peak with a much higher requirement for memory technology. As is well known, better data storage is mostly achieved by miniaturization. However, as the size of the memory device is reduced, a series of problems, such as drain gate‐induced leakage, greatly hinder the performance of memory units. To meet the increasing demands of information technology, novel and high‐performance memory is urgently needed. Fortunately, emerging memory technologies are expected to improve memory performance and drive the information revolution. This review will focus on the progress of several emerging memory technologies, including two‐dimensional material‐based memories, resistance random access memory (RRAM), magnetic random access memory (MRAM), and phase‐change random access memory (PCRAM). Advantages, mechanisms, and applications of these diverse memory technologies will be discussed in this review.

Physically unclonable function (PUF) and true random number generator (TRNG) are critical primitives to provide lightweight hardware protection. As area is tightly restricted in IoT applications, merging PUF and TRNG is a novel trend to achieve higher area efficiency. In this work, a novel tri-functional module is proposed and experimental demonstrated using RRAM for the first time. A two-phase forming process is designed to generate and store PUF ID utilizing the impact of different forming conditions on the switching window. As PUF ID is stored by the switching window, instead of a fixed resistance, PUF cells can be written to low resistance state and high resistance state as usual, and can be used as memory and TRNG. The inter-Hamming distance of the generated PUF IDs approaches 0.5, and with the majority voting readout strategy, low BER can be achieved in a wide range of temperatures from -40°C to 125°C. TRNG produces the true random numbers based on the parity of the number of pulses consumed in a write-zero process. The generated random numbers are uniform and uncorrelated after XORed, and the statistical randomness is verified by NIST SP800-22 tests.

Memristor as the fourth basic element of electric circuits has drawn substantial attention for developing future computing technologies. Sun et al. report the progress and the challenges facing researchers on understanding memristive switching, and advocate continuous studies using a synergistic approach.

The understanding of the retention and endurance degradation behavior of different levels of filamentary analog RRAM is critical for the development of the neuromorphic computing. This paper investigates the conductance distribution of different levels during retention and endurance tests. The low conductance states and high conductance states change from the normal distribution at the beginning to asymmetric skewed distribution with baking time increasing. But intermediate states remain the normal distribution. A model is proposed to predict the conductance evolution of different levels. It is also found that endurance lifetime depends on the ratio and position of endurance window. The longer endurance lifetime is attributed to switching in a smaller high-C window. Physical mechanism of endurance degradation is discussed.

Abstract High‐performance selector devices are essential for emerging nonvolatile memories to implement high‐density memory storage and large‐scale neuromorphic computing. Device uniformity is one of the key challenges which limit the practical applications of threshold switching selectors. Here, high‐uniformity threshold switching HfO2‐based selectors are fabricated by using e‐beam lithography to pattern controllable Ag nanodots (NDs) with high order and uniform size in the cross‐point region. The selectors exhibit excellent bidirectional threshold switching performance, including low leakage current (108), high endurance (>108 cycles), and fast switching speed (≈75 ns). The patterned Ag NDs in the selector help control the number of Ag atoms diffusing into HfO2 and confine the positions to form reproducible filaments. According to the statistical analysis, the Ag NDs selectors show much smaller cycle‐to‐cycle and device‐to‐device variations (CV < 10%) compared to control samples with nonpatterned Ag thin film. Furthermore, when integrating the Ag NDs selector with resistive switching memory in one‐selector‐one‐resistor (1S1R) structure, the reduced selector variation helps significantly reduce the bit error rate in 1S1R crossbar array. The high‐uniformity Ag NDs selectors offer great potential in the fabrication of large‐scale 1S1R crossbar arrays for future memory and neuromorphic computing applications.

In this work, a metal gate with a high effective work function (Weff) that is suitable for junctionless field-effect transistors (JLFETs) has been fabricated. Weff is modulated by inserting an Al interfacial layer with different thicknesses between the HfO2 dielectric layer and the Pt gate metal. Transmission electron microscopy together with capacitance–voltage (C–V) measurement is used to investigate the underlying mechanism of this phenomenon. It is suggested that the oxygen scavenging from HfO2 by the Al layer leads to the formation of interface dipoles, which effectively modulate Weff. By varying the Al layer thickness, it is found that Weff first increases and then decreases as the Al thickness increases above ∼2.5 nm, and the largest increase in Weff is about 0.56 eV. Based on these results, our work provides a useful method using interface dipoles to adjust Weff to the desired value for JLFETs, which is otherwise difficult to achieve using a single metal.

Abstract By introducing a capacitor in series (CST), a self‐terminated (ST) operation scheme is proposed to achieve high‐parallel forming of resistive random access memory (RRAM) array with reduced time and energy consumption. Once the RRAM cell is switched to the low‐resistance state, the current is automatically cut off by the capacitor, which can significantly improve the parallelism and energy efficiency. The wire capacitance of interconnect (Cwire) can be utilized as CST, which means there is no addition circuit or process expense for the proposed ST scheme. After successful experimental verification of the proposed ST operation scheme in 1 kb RRAM array, the performance of 1 Gb RRAM memory is evaluated, which shows × 103 improvement in forming time (from 0.6 h to 0.84 s) and × 104 improvement in energy consumption. Moreover, by experimentally leveraging the operation scheme for array forming, the operation current is reduced in subsequent switching process without deteriorating the device reliability, which demonstrates the feasibility of the proposed ST operation scheme and its potential in low power applications.

Here we provide a perspective concept of neurohybrid memristive chip based on the combination of living neural networks cultivated in microfluidic/microelectrode system, metal-oxide memristive devices or arrays integrated with mixed-signal CMOS layer to control the analog memristive circuits, process the decoded information, and arrange a feedback stimulation of biological culture as parts of a bidirectional neurointerface. Our main focus is on the state-of-the-art approaches for cultivation and spatial ordering of the network of dissociated hippocampal neuron cells, fabrication of a large-scale cross-bar array of memristive devices tailored using device engineering, resistive state programming, or non-linear dynamics, as well as hardware implementation of spiking neural networks (SNNs) based on the arrays of memristive devices and integrated CMOS electronics. The concept represents an example of a brain-on-chip system belonging to a more general class of memristive neurohybrid systems for a new-generation robotics, artificial intelligence, and personalized medicine, discussed in the framework of the proposed roadmap for the next decade period.

Though memristors can potentially emulate neuron and synapse functionality, useful signal energy is lost to Joule heating. Here, the authors demonstrate neuro-transistors with a pseudo-memcapacitive gate that actively process signals via energy-efficient capacitively-coupled neural networks.

Abstract Neuromorphic systems consisting of artificial neurons and synapses can process complex information with high efficiency to overcome the bottleneck of von Neumann architecture. Artificial neurons are essentially required to possess functions such as leaky integrate‐and‐fire and output spike. However, previous reported artificial neurons typically have high operation voltage and large leakage current, leading to significant power consumption, which is contrary to the energy‐efficient biological model. Here, an oscillatory neuron based on Ag filamentary threshold switching memristor (TS) that has a low operation voltage (108 cycles). Being connected to an external resistor or a resistive switching memristor (RS) as synaptic weight, the TS clearly demonstrates self‐oscillation behavior once the input pulse voltage exceeds the threshold voltage. Meanwhile, the oscillation frequency is proportional to the input pulse voltage and the conductance of RS synapse, which can be used to integrate the weighted sum current. As an energy‐efficient memristor‐based spiking neural network, this combination of TS oscillatory neuron with RS synapse is further evaluated for image recognition achieving an accuracy of 79.2 ± 2.4% for CIFAR‐10 subset.

The development of humanoid robots with artificial intelligence calls for smart solutions for tactile sensing systems that respond to dynamic changes in the environment. Here, Yoon et al. emulate non-adaption and sensitization function of a nociceptor—a sensory neuron—using diffusive oxide-based memristors.

Abstract A nitridation treatment technology with a urea/ammonia complex nitrogen source improved resistive switching property in HfO2-based resistive random access memory (RRAM). The nitridation treatment produced a high performance and reliable device which results in superior endurance (more than 109 cycles) and a self-compliance effect. Thus, the current conduction mechanism changed due to defect passivation by nitrogen atoms in the HfO2 thin film. At a high resistance state (HRS), it transferred to Schottky emission from Poole-Frenkel in HfO2-based RRAM. At low resistance state (LRS), the current conduction mechanism was space charge limited current (SCLC) after the nitridation treatment, which suggests that the nitrogen atoms form Hf–N–Ox vacancy clusters (Vo +) which limit electron movement through the switching layer.

This Special Issue of the IEEE Journal of Electron Devices Society is a selection of papers presented at the 2021 IEEE Electron Devices Technology and Manufacturing (EDTM) Conference. Sponsored by IEEE Electron Devices Society (EDS), IEEE EDTM is a premier conference providing a unique forum for discussions on a broad range of device/manufacturing-related topics. EDTM rotates among the hot-hubs of semiconductor manufacturing in Asia. EDTM2021 was successfully held in Chengdu, China, during March 9-12, 2021. The Theme for EDTM2021 was Intelligent Technologies for Smart and Connected Life. Due to the pandemic, EDTM2021 was held in hybrid formats including a large onsite/in-person gathering and a virtual conference. EDTM2021 was a four-day conference comprising a one-day tutorial/short course/workshop event and a three-day technical program including both oral and poster sessions. On Day-1, EDTM2021 was kicked off with two parallel tutorial tracks and four concurrent short course sessions. The two tutorial series focused on “Flexible electronics + Display” and “Future Communication and Computing.” The four short course sessions covered “Advanced Memories and Emerging Applications,” “Quantum Computing Technologies,” “Advanced Processing and Manufacturing” and “Ultra/Wide Bandgap Power Electronics.” Total twelve lectures were given by globally renowned experts. The highlight on Day-1 also includes the “HIR Workshop Organizing Committee” organized by the IEEE Heterogeneous Integration Roadmap Committee and featured by eighteen experts from around the globe discussing the advances, challenges and future of HI technologies. EDTM2021 Technical Program includes six Keynote Speakers talking about various hot topics, including Dr. Haijun Zhao (Co-CEO of SMIC) on “Creating Values through Innovations on Mature Nodes of Technologies of Integrated Circuits,” Prof. Xiang Zhang (President, University of Hong Kong) on “How to build a camera with highest resolution: a photonics perspective,” Mr. Teruo Hirayama (Executive Chief Engineer, Sony Corp.) on “The power of image sensors for innovation,” Prof. Arokia Nathan (University of Cambridge) on “Thin Film Transistor Architectures for Advanced Analog Signal Processing,” Prof. Ru Huang (Vice President, Peking University) on “Ferroelectric-based device: revived as a low-power technology booster for diverse applications” and Dr. Jeff Xu (Director, HiSilicon Research) on “Ubiquitous Computing Drives Future Semiconductor Technology.” The Plenary was closed with a Closing Banquet Speech given by Prof. Ilesanmi Adesida (Provost, Nazabaryev University) entitled “The Development of an International Research University in the Big Steppe of Kazakhstan.” EDTM2021 Technical Program core contains about 289 technical papers accepted after strict peer reviewing, including 172 oral (organized into 36 Sessions) and 117 interactive presentations. EDTM2021 had a total registered attendance of 800+, including 492 for the Technical Program (283 in-person and 209 virtual), 156 for Tutorials and 158 for Short Courses.

Using chips that mimic the human brain to perform cognitive tasks, namely neuromorphic computing, calls for low power and high efficiency hardware. Here, Yaoet al. show on-chip analogue weight storage by integrating non-volatile resistive memory into a CMOS platform and test it in facial recognition.

Spiking Neural Networks (SNNs) offer great potential to promote both the performance and efficiency of real-world computing systems, considering the biological plausibility of SNNs. The emerging analog Resistive Random Access Memory (RRAM) devices have drawn increasing interest as potential neuromorphic hardware for implementing practical SNNs. In this article, we propose a novel training approach (called greedy training) for SNNs by diluting spike events on the temporal dimension with necessary controls on input encoding phase switching, endowing SNNs with the ability to cooperate with the inevitable conductance variations of RRAM devices. The SNNs could utilize Spike-Timing-Dependent Plasticity (STDP) as the unsupervised learning rule, and this plasticity has been observed on our one-transistor-one-resistor (1T1R) RRAM devices under voltage pulses with designed waveforms. We have also conducted handwritten digit recognition task simulations on MNIST dataset. The results show that the unsupervised SNNs trained by the proposed method could mitigate the requirement for the number of gradual levels of RRAM devices, and also have immunity to both cycle-to-cycle and device-to-device RRAM conductance variations. Unsupervised SNNs trained by the proposed methods could cooperate with real RRAM devices with non-ideal behaviors better, promising high feasibility of RRAM array based neuromorphic systems for online training.

Abstract Leakage interference between memory cells is the primary obstacle for enlarging X‐point memory arrays. Metal‐filament threshold switches, possessing excellent selectivity and low leakage current, are developed in series with memory cells to reduce sneak path current and lower power consumption. However, these selectors typically have limited on‐state currents (≤10 µA), which are insufficient for memory RESET operations. Here, a strategy is proposed to achieve sufficiently large RESET current (≈2.3 mA) by introducing highly ordered Ag nanodots to the threshold switch. Compared to the Ag thin film case, Ag nanodots as active electrode could avoid excessive Ag atoms migration into solid electrolyte during operations, which causes stable conductive filament growth. Furthermore, Ag nanodots with rapid thermal processing contribute to forming multiple weak Ag filaments at a lower voltage and then spontaneous rupture as the applied voltage reduced, according to quantized conductance and simulation analysis. Impressively, the Ag nanodots based threshold switch, which is bidirectional and truly electroforming‐free, demonstrates extremely high selectivity >109, ultralow leakage current

The parallel updating scheme of RRAM-based analog neuromorphic systems based on sign stochastic gradient descent (SGD) can dramatically accelerate the training of neural networks. However, sign SGD can decrease accuracy. Also, some non-ideal factors of RRAM devices, such as intrinsic variations and the quantity of intermediate states, may significantly damage their convergence. In this paper, we analyzed the effects of these issues on the parallel updating scheme and found that it performed poorly on the task of MNIST recognition when the number of intermediate states was limited or the variation was too large. Thus, we propose a weighted synapse method to optimize the parallel updating scheme. Weighted synapses consist of major and minor synapses with different gain factors. Such a method can be widely used in RRAM-based analog neuromorphic systems to increase the number of equivalent intermediate states exponentially. The proposed method also generates a more suitable ΔW, diminishing the distortion caused by sign SGD. Unlike when several RRAM cells are combined to achieve higher resolution, there are no carry operations for weighted synapses, even if a saturation on the minor synapses occurs. The proposed method also simplifies the circuit overhead, rendering it highly suitable to the parallel updating scheme. With the aid of weighted synapses, convergence is highly optimized, and the error rate decreases significantly. Weighted synapses are also robust against the intrinsic variations of RRAM devices.