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The article addresses a novel topology of analog voltage comparator capable of processing the input voltage in rail-to-rail range. We propose two different innovative comparator topologies. One topology is employing a standard “gate-driven” (GD) control of MOS transistors and designed in 65 nm CMOS technology. The other one, designed in 130 nm CMOS technology, uses rather unconventional “bulk-driven” (BD) control of active devices in the circuit. Each presented circuit topology has its own pros and cons, however both are suitable and actually aimed for ultra low-voltage (ULV) and/or ultra low-power (ULP) applications. The proposed comparator designs have been extensively analyzed for robustness and parameter stability across all fabrication process corners, a wide temperature range (from -20 ◦ C to 85 ◦ C), and for random process variations, as well. Both presented comparator designs can reliably operate with power consumption in nano-watt range without any fuse trimming or calibration, as the proof of concept has been confirmed by measurements performed on prototype chips.

In this paper, indirect methods suitable for sensing the output load current (or current consumption) of analog circuits were studied and analyzed. The main focus was paid on approaches that can be implemented on a chip. The proposed approach for sensing the output current of a DC-DC converter is based on measuring the slope of a voltage sensed by an output bypass capacitor. Such an indirect sensing approach shows better efficiency than a common shunt-resistor-based sensing method. The presented approach was used in a flyback type of DC-DC converter. Simulation results prove better voltage conversion efficiency using the proposed indirect measurement approach if compared to existing alternatives.

This paper deals with design of a digital circuit for the Maximum Power Point Tracking (MPPT), especially analysis of its energy consumption. The circuit is based on a widely used direct tuning algorithm called Perturb & Observe (P&O). The digital circuit was designed at Register Transfer Level (RTL) using the descriptive language Verilog. The proposed digital circuit was synthesized in standard 130 nm CMOS technology, where also Place and Route (P&R) was performed.