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Convolutional Neural Networks has (CNN) have been widely used in various Internet-of-Things (IoT) applications to offer smart solutions in our daily lives. Many hardware accelerators were proposed to speed up CNN, so that it can be used in the IoT sensor nodes. Recently, octave convolution was proposed to remove spatial redundancy from input feature maps, thus reducing the CNN computation and memory cost. Although octave CNN is an attractive candidate for IoT applications, it cannot replace regular CNN, which is already widely used in many applications. Hence, it is desirable to have a hardware accelerator that can flexibly support both regular and octave convolution. In this work, we present the first compact and flexible CNN accelerator on an Field-Programmable-Gate-Array (FPGA), which supports normal, pointwise and depthwise convolutions for state-of-the-art octave convolution, as well as the existing regular convolution. To ensure efficient accelerator utilization, a novel adaptive scheduling scheme is presented to schedule the number of computation tasks based on varying feature map dimensions across CNN layers. A novel integration technique is presented to execute the varying computational patterns in octave convolution due to multiple branching in a single computation unit. An efficient memory scheme and execution scheduling for octave convolution are also proposed to overlap the long data fetch time with the on-going octave computation for better overall computation performance. Comparing to other state-of-the-art work, our proposed accelerator achieved 1.98x higher computation density for MobileNetV2 implementation on XC7ZU9EG, as well as about 83.9% lesser power for ResNet-50 implementation on VU9P.

Practical deployment of convolutional neural net?work (CNN) and cryptography algorithm on constrained devices are challenging due to the huge computation and memory requirement. Developing separate hardware accelerator for AI and cryptography incur large area consumption, which is not desirable in many applications. This paper proposes a viable solution to this issue by expressing the CNN and cryptography as Generic-Matrix-Multiplication (GEMM) operations and map them to the same accelerator for reduced hardware consumption. A novel systolic tensor array (STA) design was proposed to reduce the data movement, effectively reducing the operand registers by 2×. Two novel techniques, input layer extension and polynomial factorization, are proposed to mitigate the under-utilization issue found in existing STA architecture. Additionally, the Tensor Processing Element (TPE) is fused using DSP unit to reduce the Look-Up Table (LUT) and Flip-Flops (FF) consumption for implementing multipliers. On top of that, a novel memory efficient factorization technique is proposed to allow computation of polynomial convolution on the same STA. Experimental results show that Cryptensor achieved 22.3% better throughput for VGG-16 implementation on XC7Z020 FPGA; 95.0% lesser LUT when implementing on XC7Z045 compared to state-of-the-art result. Cryptensor can also flexibly support multiple security levels in NTRU scheme, with no additional hardware. The proposed hardware unifies the computation of two different domains that are critical for IoT applications, which greatly reduces the hardware consumption on edge nodes.

Neural networks have become deeper in recent years and this has improved its capacity to handle more complex tasks. However, deep neural network has more parameters and is easier to overfit, especially when training samples are insufficient. In this paper, we present a new regularization technique called batch contrastive regularization to improve generalization performance. The loss function is based on contrastive loss which enforces intra-class compactness and inter-class separability of batch samples. We explore three different contrastive losses: (1) the center contrastive loss which regularizes based on distances between data points and their corresponding class centroid, (2) the sample contrastive loss which is based on batch sample-pair distances, and (3) the multicenter loss which is similar to center contrastive loss except that the cluster centers are discovered from training. The proposed network has two heads, one for classification and the other for regularization. The regularization head is discarded during inference. We also introduce bag sampling to ensure that all classes in a batch are well represented. The performance of the proposed architecture is evaluated on the CIFAR-10 and CIFAR-100 datasets. Our experiments show that network regularized by batch contrastive loss display impressive generalization performance over a wide variety of classes, yielding more than 11% improvement for ResNet50 on CIFAR-100 when trained from scratch.

A large portion of crops are lost to plant diseases each year worldwide. In this study, a mobile application for detecting and classifying plant disease using deep learning object detection model was developed. The proposed mobile application utilizes Faster R-CNN object detector with Inception-v2 backbone network to achieve robust and efficient detection. Experiments on grape disease images demonstrated that the proposed application is able to achieve an accuracy of 97.9% while running solely on a smartphone without connecting to a server. The proposed mobile application can serve as an aid to farmers and crop growers who have little or no knowledge about plant diseases for early disease detection and control and therefore can reduce losses and prevent further spreading of the disease.

Action recognition is one of the popular research areas in computer vision because it can be applied to solve many problems especially in security surveillance, behavior analysis, healthcare and so on. Some of the well-known Convolutional Neural Network (CNN) in action classification using 3D convolution are C3D, I3D and R(2 + 1)D. These 3D CNNs assume that the spatial and temporal dimensions of motion are uniform where the 3D filters are uniformly shaped. However, the path in motion can be in any directions and a uniform shape filter might not be able to capture nonuniform spatial motion and this limits the performance of the classification. To address the above problem, we incorporate a 3D deformable filter in a C3D network for action classification. The deformable convolution adds offsets to the regular grid sampling locations in the standard convolution resulting in non-uniform sampling location. We will also investigate the performance of the network when apply the 3D deformable convolution in different layers and the effect of different dilation size of the 3D deformable filter. UCF101 dataset is used in the experiments. From our experiments, it is found that applying the deformable convolution in lower layer yield better result compare to other layers. Our experiment shows that if we put the deformable convolution in Conv1a, the accuracy achieved is 48.50%.

Automatic hand posture detection of smartphone users is important for adaptive user interface design, context aware application development, and activity analysis. This paper presents a method for hand posture and phone placement detection from data produced by accelerometer, magnetometer and gyroscope of a smartphone using LSTM networks. Real-time testing results indicated that LSTM network is effective in hand posture and phone placement prediction, and the proposed method outperformed existing methods by significant margins.

Due to ubiquitous information requirements, market interest in mobile business intelligence (BI) has grown markedly. However, mobile BI market is a relatively new area that has been driven primarily by the IT industry. Yet, there is a lack of systematic study on the critical success factors for mobile BI. This research reviews the state-of-the-art of mobile BI, and explores the critical success factors based on a rigorous examination of the academic and practitioner literature. The study reveals that critical success factors of mobile BI generally fall into four key dimensions, namely security, mobile technology, system content and quality, and organisational support perspectives. The various research findings will be useful to organisations which are considering or undertaking mobile business intelligence initiatives.

The overwhelming amount of multimedia entities shared over the web has given rise to the need for semantic identification and classification of these entities. Numerous research efforts have tackled this problem by developing advanced content analysis techniques as well as leveraging on readily available tags, scripts, and blogs related to these multimedia entities. However, in many cases, especially for event detection and action recognition, the research efforts were hampered by the lack of large scale publicly available benchmarks. To address this problem, this paper presents a large-scale movie corpus named MovieBase that covers full length feature movies as well as huge volume of movie-related video clips downloaded from YouTube. The corpus is designed for research in event detection and action recognition. It offers over 71 hours of videos with a total of 69,129 shots. The corpus has been hand-labeled according to 7 audio and 11 visual concept tags to semantically define 11 event categories under the romantic and violence scenes. The corpus comes with a set of pre-extracted low-level visual, motion, audio as well as high-level features. Related results are furnished as a baseline for the movie event detection task.

With the increased complexity of applications, parallel computing has proved to be an alternative to supercomputing in solving large problems. However developing parallel applications is more difficult compared to sequential programming. Visual technologies can be employed to aid the multi-dimensional tasks of parallel programming. This paper presents a case study of the use of an integrated visual programming environment in creating parallel applications. Techniques for the hierarchical construction of parallel programs are presented, together with an evaluation of the performance of the generated code for a matrix multiplication application.

The performance and cost-performance benefits of parallel systems make them attractive platforms for many applications. But, these are unfortunately offset by the difficulties of programming parallel computers. Therefore, programming tools are the key to achieve greater success in developing applications for parallel architectures. This paper describes a new tool, VPEcons, for parallel programming development. It uses graphics to assist in the design of parallel programs. To facilitate the portability of the constructor, a VPEcons Builder has also been developed. It is a tool for creating basic component blocks and binding an existing language to the blocks created. The usefulness of the constructor is demonstrated with a parallel discrete-event simulation example and by comparing it with other visual parallel programming tools. >