Search

Based on two published UV absorbing molecules 2-(5′-tert-butyl-2′-hydroxyl)benzotriazole (Tinuvin-PS) and hydroxybenzophenone (HBP), both having characteristic absorption capability, a refined UV absorber, 2-(3′-benzoyl-2′-hydroxy-5′-tert-butylphenyl)benzotriazole, has been synthesized. This new UV absorber exhibits a wider absorption range and better thermal stability compared to either Tinuvin-PS and HBP and a higher absorption efficiency in the UV-C range. Theoretical studies reveal that the UV-C absorption arises from the electron density transfer from the Tinuvin-PS moiety to the HBP moiety and the enhanced absorption efficiency is ascribed to the presence of the carbonyl's π system.

The pi-nature of a CF3 group can be understood through analysis of its bond orbitals (BOs) mixed into the pi-type molecular orbitals of CF3-substituted Ir(ppy)2MDPA+ complexes (ppy=2-phenyl-pyridine and MDPA=methylated 2,2′-dipyridyl amine). It has been found that, through this natural bond orbital analysis, the parent’s molecular orbitals (MOs) can be stabilized by χρ*CF BO via negative hyperconjugation and, simultaneously, destabilized by electron lp(F) BO. Since these two competing pi-effects are virtually counterbalanced as indicated by the vanishing values of crystal orbital overlap populations, the chemical substitution strategy originated from lowering of HOMO by using this electron-withdrawing CF3 group has been found effective in color-tuning to blue region. Based on reduced shielding effect due to de- creased χρ-electron density, the reported position dependent CF3-substitution effects on pi-type MOs can also be understood through HOMO/LUMO wavefunction analysis.

Background: The resuscitation guidelines indicate pre-arrival dispatcher-assisted telephone CPR (DATCPR) instructions and measurement to increase the proportion of bystander CPR (BCPR), however the impact of those guidelines on survival is not well known. Objective: To describe the impact of a comprehensive bundle of DATCPR on BCPR and survival from OHCA in a horizontal computerized-aided dispatch (CAD) system. Methods: A centralize CAD system in a metropolitan EMS is studied. Routinely in system the time from call to ambulance dispatch should be within 60 seconds. The audio recordings of confirmed OHCAs were reviewed using a standardized format linked with EMS and hospital process and outcome data. The proportions of BCPR and survival six months after implementation (P1) of a bundle that included guideline-based protocol changes, staff training, computerized audit, feedback to providers and leadership rebuilt are compared with that of the same month period in the prior year as control group (P0), using regression analysis for statistics. Results: There were 1437 OHCAs [665 P0, 772 P1; 64% male, median age 62 (IQR: 47-74)](Table 1). The rate of BCPR went from 20.6% in P0 to 35.0% in P1 (p Conclusions: The implementation of a comprehensive bundle of DATCPR in a metropolitan horizontal dispatch system was associated with significant improvements in the rates of BCPR and good neurologic outcome after OHCA.

Thermal laser stimulation (TLS) implemented under testing has become an important failure analysis technique for System-on-Chip (SoCs). This technique ensures that devices under testing (DUT) can enter particular modes, which turn on certain circuit blocks when performing TLS. However, from foundry's perspective, TLS operated under testing may not be a cost-effective solution as numerous design and test resources are required. This paper proposes a novel dual source heating system which can localize defects without utilizing any vectors by using a thermal laser in combination with a heating plate connected to a temperature controller. In this study, a defective SoC was globally heated using the heating plate to enhance the leakage path by changing the properties of the chip. Meanwhile, active or passive devices inside the defective SoC were locally heated using the thermal laser to enhance the defect detection capability by changing the electrical behaviors of the active or passive devices. Using this technique, a silicon defect located in an embedded functional circuit block of the defective SoC was successfully isolated without pausing the sample at any certain vectors.

Electrical characteristic changes in scaled MOSFET devices have been widely reported due to electron beam (EB) irradiation. For local oxidation of silicon (LOCOS) devices, the effects of EB-induced damage when performing measurements using an SEM based nanoproer, however, have rarely been reported. EB penetration into the dielectrics, resulting in the modification of the physical properties of the dielectric layer, could be a concern, not only for scaled devices, but also for LOCOS devices. This study reveals that the effect of EB on LOCOS devices can be measured using a scanning electron microscope (SEM) based nanoprober with inducing electrical characteristic changes. These changes are accounted for by the hole trapping at the birdsbeak, which has a significant effect on both the junction electrical characteristics and punchthrough characteristics in LOCOS isolation structures when an SEM is employed for probe guidance. Further, some preliminary experimental results, not included in this paper, show that lowering the EB acceleration voltage is found to not be able to significantly eliminate the effects of EB-induced damage during device inspections in failure analysis procedures. More advanced studies are currently under investigation.

It has been widely reported that floating gate irradiation using a charged beam can shift device parameters with the scaling of the devices [1–4]. For high voltage (HV) devices, the effects of electron beam (EB) induced damage, however, have not been reported. This paper describes how charge damage during EB exposure should also be considered for high voltage (HV) devices when scanning electron microscope (SEM) is employed for probe guidance. In this study, the effects of EB cathode potential on CMOS transistor threshold voltage and off-state current are investigated using HV, middle voltage (MV), and low voltage (LV) devices. The experimental results show that, to avoid damage, the acceleration voltage of EB should be lower.

A soft failure, which is recoverable and sensitive to certain stresses, such as voltage, temperature and light, is defined as a failure, fault, defect, or error that results in a shift in the operating margin of a device. Several studies have been conducted into voltage or temperature dependent failures [1–3]. Research into light sensitive failures, however, has seldom been reported, as it is more difficult to isolate defects which are sensitive to light. Although certain global fault isolation techniques, such as photoelectric laser stimulation (PLS) have been developed to localize a wide range of potentially light sensitive defects, by means of the perturbation of the integrated circuit (IC) properties through carrier generation in the silicon, PLS cannot perform an exact failure localization on a single transistor or junction because of limited spatial resolution. This paper describes the use of a conductive atomic force microscope (C-AFM) within the failure analysis (FA) flow as a local fault isolation method in order to generate a more reliable failure hypothesis and successful physical root cause visualization for light-sensitive defects, and, using this technique, such failures, which pose potential reliability issues for devices as the affected circuit degrades over time or under stress, can be easily screened before any quality assurance test.

The use of nanoprobing techniques to accomplish transistor parametric data extraction has been widely reported as a method of failure analysis in nanometer scale science and technology. Certain failure mechanisms causing parametric transistor fails are, however, not always successfully identified, even using advanced imaging tools, such as transmission electron microscopy (TEM). Therefore, additional techniques are needed that can reveal the physical root cause of the electrical defects. In this paper, an approach using dopant selective etching of samples for TEM is adopted to enable visualization of invisible defects embedded in the poly gate.

The intrinsic carrier concentration n i is highly temperature dependent in non-degenerate semiconductors. At high temperatures, thermally generated electron-hole pairs contribute to the carrier concentrations. As a result, the generation of free carriers can be achieved through light-to-heat conversion using near-infrared (NIR) laser. This paper describes the use of the thermal laser stimulation (TLS) technique to modify the electrical properties of a heated passive device so that the direct failure location can be revealed in order to clarify the cause of the iddq leakage that will disappear during high temperature tests.

The photoperturbation effects induced via a Conductive Atomic Force Microscope (C-AFM) laser beam, in which the surface photovoltaic effect and the carrier injection effect included in the photoperturbation can cause significant deterioration in the characterization accuracy have been widely investigated [1–5]. This study, however, successfully demonstrates how to take advantage of these non-negligible photoelectric effects to isolate marginally defective gates, which are usually difficult to uncover using the traditional approach of passive voltage contrast (PVC) carried out using a scanning electron microscope (SEM) or focused ion beam (FIB), or even when using an advanced SEM-based nanoprobing technique. Using this technique, such failures, which pose potential reliability issues on devices as the affected circuit degrades over time or under stress, can be easily screened before any quality assurance test.

The method of substrate isolation in a typical CMOS HV technology with the addition of a deep nwell (DNW) is commonly applied in order to minimize the effect of disturbance in the substrate potential. The difficulties in identifying the true leakage path are, however, increasing as the noise current flows from this complex well structure with DNW employed in CMOS HV technology. This paper describes the use of nanoprobing and scanning electron microscope (SEM) doping contrast techniques to quickly and precisely pinpoint the leakage path.

This paper presents insights into the mechanisms of counter doping and gate depletion due to the lateral diffusion of dopants in embedded FLASH technology. Core SRAM device behavior is modified by the thermal budget needed to process the specific FLASH dielectrics. Using a nanoprobe technique, the MOS characteristics of failed and good bits used as a reference in actual SRAM cells were measured directly. In the worst cases, it was confirmed that the on-state current of a PMOS was about three orders of magnitude smaller than that of normal bits, and the threshold voltage was of about 0.9V higher. A selective etching technique using a KOH solution showed these degradations were caused by local gate depletion. The fabrication process flow shows that the thermal treatment used to form the rapid thermal oxidation layer, causing additional thermal budget, can lead to lateral As-dopant diffusion into a B-doped gate. This diffusion can cause work-function shift, as well as the formation of a depletion capacitor at the polysilicon gate oxide interface, while the MOS is biased. Adjusting the N+ implant boundary for the second poly layer to increase the margin has been found to be quite effective in improving the on-state current degradation and increasing yield.

The use of scanning probe microscopes (SPM), such as conductive atomic force microscope (C-AFM) and scanning capacitance microscope (SCM) have been widely reported as a method of failure analysis in nanometer scale science and technology. This paper will demonstrate the use of the C-AFM to identify the true SRAM leakage path in CMOS process with the addition of a deep n-well (DNW) module. After taking electrical measurements, the SCM technique is utilized to identify and understand the physical root cause of the electrical failure.

Ion implantation is one of the most common steps in the manufacture of integrated circuits. The characterization and visualization of process-induced particle contamination acting as masks that block implantation especially when the defects are not in a specific area of a chip takes a lot of effort. This paper describes the use of a Conductive Atomic Force Microscope (C-AFM) technique coupled with wet chemical etching analysis to quickly make different implants visible at low cost.

A beam bounce technique in a conductive atomic force microscope (C-AFM) system is usually used to enable the probe head to measure extremely small movements of the cantilever as it is moved across the surface of the sample. However, the laser beam used for the beam bounce also gives rise to the photoelectric effect while we are measuring electrical characteristics of a device. The photoelectric effect occurring in NMOSFETs caused by a laser beam used in the C-AFM system has been reported [1]. In this study, the photoelectric effect occurring in PMOSFETs will be discussed. An example that an invisible implant defect in a PMOSFET was successfully identified using the C-AFM based on the measured electrical characteristics and the bipolar phototransistor action models will also be introduced.

The use of a scanning probe microscope (SPM), such as a conductive atomic force microscope (C-AFM) has been widely reported as a method of failure analysis in nanometer scale science and technology [1-6]. A beam bounce technique is usually used to enable the probe head to measure extremely small movements of the cantilever as it is moved across the surface of the sample. However, the laser beam used for a beam bounce also gives rise to the photoelectric effect while we are measuring the electrical characteristics of a device, such as a pn junction. In this paper, the photocurrent for a device caused by photon illumination was quantitatively evaluated. In addition, this paper also presents an example of an application of the C-AFM as a tool for the failure analysis of trap defects by taking advantage of the photoelectric effect.

SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture. However, the success rate of defect detection, especially for soft single-column failures, is decreasing when traditional physical failure analysis (PFA) with only the bitmap is available for guidance. This is due to a variety of invisible or undetectable defects that cause leakage in the device. In order to understand the leakage behavior in advanced high voltage (HV) processes, a Conductive Atomic Force Microscope (C-AFM) [1-4] is introduced to perform junction-level fault isolation prior to attempting PFA. According to J. P. Morniroli [5], crystalline defects affect convergent-beam electron diffraction (CBED) and large angle convergent-beam electron diffraction (LACBED) patterns, so CBED and LACBED techniques were also applied to the specimens containing dislocations to allow further characterization of these defects. In this study quantified data extracted using the C-AFM is also used to establish a connection between the failure mechanism discovered and the soft single column failure mode.

The importance of understanding mismatched behavior in SRAM devices has increased as the technology node has shrunk below 100nm. Using the nanoprobe technique [1-3], the MOS characteristics of failure bits in actual SRAM cells have been directly measured. After transistors that are failing were identified, the best approach for identifying nanoscale defects was determined. In this study, several types of nanoscale defects, such as offset spacer residue, salicide missing from the active area, doping missing from the channel, gate oxide defects, contact barrier layer residue, and severed poly-gate silicide were successfully discovered.

It has been long recognized that SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture and simplified approach using memory bitmapping. However, the success rate of defect detection, especially for soft single-column failures, which is one of the most complex failure modes of an SRAM failure, is decreasing when using traditional physical failure analysis (PFA) with only the bitmap available for guidance due to a variety of invisible or undetectable defects that cause a leakage behavior in the device. In order to understand the leakage behavior in advanced high voltage (HV) processes, conductive atomic force microscope (C-AFM) [1-5] is introduced to perform junction-level fault isolation prior to attempting PFA. In this study, the quantified data extracted using the C-AFM can also be used to establish a connection between the failure mechanism discovered and the soft single column failure mode.

The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.

The importance of understanding asymmetrical behaviour in SRAM has increased as the technology node shrinks below 100 nm. Single bit failure can possibly be caused by the malfunction of any of the six transistors in a standard SRAM cell. In order to understand the asymmetrical behaviour in advanced nano SRAM devices, nanoprobing is introduced to perform transistor level fault isolation prior to attempting physical failure analysis (PFA)

Single column failure [1], one of the complex failure modes in SRAM is possibly induced by multiform defect types at diverse locations. Especially, soft single column failure is of great complexity. As physical failure analysis (PFA) is expensive and time-consuming, thorough electrical failure analysis (EFA) is needed to precisely localize the failing area to greater precision before PFA. The methodology involves testing for failure mode validation, understanding the circuit and using EFA tools such as IR-OBIRCH (InfraRed-Optical Beam Induced Resistance CHange) and MCT (MerCad Telluride, HgCdTe) for analysis. However, the electrical failure signature for soft single column failure is usually marginal, so additional techniques are needed to obtain accurate isolation and electrical characterization instead of blindly looking around. Thus in this discussion, we will also present the use of internal probing techniques like C-AFM [2] (Conductive Atomic Force Microscopy) and a nanoprobing technique [3] for characterizing electrical properties and understanding the root cause.