12 results on '"Huynh-Bao, Trong"'
Search Results
2. Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications
3. (Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs
4. Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond
5. DTCO at N7 and beyond: patterning and electrical compromises and opportunities
6. (Invited) Vertical Nanowire FET Integration and Device Aspects
7. Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
8. A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs
9. Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
10. (Keynote) Gate-All-Around Nanowire & Nanosheet FETs for Advanced, Ultra-Scaled Technologies
11. (Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs
12. Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.