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12 results on '"Huynh-Bao, Trong"'

2. Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications

Author

Huynh-Bao, Trong, primary, Veloso, Anabela, additional, Sakhare, Sushil, additional, Matagne, Philippe, additional, Ryckaert, Julien, additional, Perumkunnil, Manu, additional, Crotti, Davide, additional, Yasin, Farrukh, additional, Spessot, Alessio, additional, Furnemont, Arnaud, additional, Kar, Gouri, additional, and Mocuta, Anda, additional

Published
2019
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3. (Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Author

Veloso, Anabela, primary, Paraschiv, Vasile, additional, Vecchio, Emma, additional, Devriendt, Katia, additional, Li, Waikin, additional, Simoen, Eddy, additional, Chan, B. T., additional, Tao, Zheng, additional, Rosseel, Erik, additional, Loo, Roger, additional, Milenin, Alexey P., additional, Kunert, Bernardette, additional, Teugels, Lieve, additional, Sebaai, Farid, additional, Lorant, Christophe, additional, van Dorp, Dennis, additional, Altamirano-Sánchez, Efraín, additional, Brus, Stephan, additional, Marien, Philippe, additional, Fleischmann, Claudia, additional, Melkonyan, Davit, additional, Huynh-Bao, Trong, additional, Eneman, Geert, additional, Hellings, Geert, additional, Sibaja-Hernandez, Arturo, additional, Matagne, Philippe, additional, Waldron, Niamh, additional, Mocuta, Dan, additional, and Collaert, Nadine, additional

Published
2017
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5. DTCO at N7 and beyond: patterning and electrical compromises and opportunities

Author

Sushil Sakhare, Aaron Thean, Huynh Bao Trong, Philippe Leray, P. Schuddinck, An Steegen, Arindam Mallik, Jürgen Bömmels, Zsolt Tokei, Abdelkarim Mercha, Kurt G. Ronse, Bharani Chava, G. McIntyre, Diederik Verkest, J. Ryckaert, Praveen Raghavan, and Yasser Sherazi

Subjects
Scheme (programming language), Computer science, Extreme ultraviolet lithography, Transistor, Process (computing), Nanotechnology, law.invention, Stack (abstract data type), law, Electronic engineering, Photolithography, Scaling, computer, computer.programming_language
Abstract

At 7nm and beyond, designers need to support scaling by identifying the most optimal patterning schemes for their designs. Moreover, designers can actively help by exploring scaling options that do not necessarily require aggressive pitch scaling. In this paper we will illustrate how MOL scheme and patterning can be optimized to achieve a dense SRAM cell; how optimizing device performance can lead to smaller standard cells; how the metal interconnect stack needs to be adjusted for unidirectional metals and how a vertical transistor can shift design paradigms. This paper demonstrates that scaling has become a joint design-technology co-optimization effort between process technology and design specialists, that expands beyond just patterning enabled dimensional scaling.

Published
2015

6. (Invited) Vertical Nanowire FET Integration and Device Aspects

Author

Veloso, Anabela, primary, Altamirano-Sánchez, Efraín, additional, Brus, Stephan, additional, Chan, B. T., additional, Cupak, Miroslav, additional, Dehan, Morin, additional, Delvaux, Christie, additional, Devriendt, Katia, additional, Eneman, Geert, additional, Ercken, Monique, additional, Huynh-Bao, Trong, additional, Ivanov, Tsvetan, additional, Matagne, Philippe, additional, Merckling, Clement, additional, Paraschiv, Vasile, additional, Ramesh, Siva, additional, Rosseel, Erik, additional, Rynders, Luc, additional, Sibaja-Hernandez, Arturo, additional, Suhard, Samuel, additional, Tao, Zheng, additional, Vecchio, Emma, additional, Waldron, Niamh, additional, Yakimets, Dmitry, additional, De Meyer, Kristin, additional, Mocuta, Dan, additional, Collaert, Nadine, additional, and Thean, Aaron, additional

Published
2016
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10. (Keynote) Gate-All-Around Nanowire & Nanosheet FETs for Advanced, Ultra-Scaled Technologies

Author

Veloso, Anabela, Matagne, Philippe, Jang, Doyoung, Huynh-Bao, Trong, Chasin, Adrian, Simoen, Eddy, Eneman, Geert, De Keersgieter, An, Mertens, Hans, and Horiguchi, Naoto

Abstract

We report on gate-all-around (GAA) vertically stacked lateral nanowires (NW) and nanosheets (NS) FET devices as promising candidates to replace finFETs and help preserve the power, performance, area, and cost (PPAC) logic roadmap for advanced sub-5nm technology nodes. In addition, GAA vertical NW/NS FETs appear particularly attractive for enabling highly dense memory cells such as ultra-scaled MRAMs with lower energy consumption and smaller access latency values. Key fabrication challenges and device features for both types of transistors will be discussed here, together with the possibility to manufacture them on the same wafer by a cost-effective, co-integration scheme to obtain simultaneously a high-performance logic platform and have increased on-chip memory content.

Published
2020
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11. (Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Author

Veloso, Anabela, Paraschiv, Vasile, Vecchio, Emma, Devriendt, Katia, Li, Waikin, Simoen, Eddy, Chan, B. T., Tao, Zheng, Rosseel, Erik, Loo, Roger, Milenin, Alexey P., Kunert, Bernardette, Teugels, Lieve, Sebaai, Farid, Lorant, Christophe, van Dorp, Dennis, Altamirano-Sánchez, Efraín, Brus, Stephan, Marien, Philippe, Fleischmann, Claudia, Melkonyan, Davit, Huynh-Bao, Trong, Eneman, Geert, Hellings, Geert, Sibaja-Hernandez, Arturo, Matagne, Philippe, Waldron, Niamh, Mocuta, Dan, and Collaert, Nadine

Abstract

This work reports on some key integration aspects for 3D devices fabrication, focusing first on the impact of thermal and plasma treatments at gate module for triple-gate finFETs and their ultimate scaling limit: gate-all-around (GAA) nanowire (NW) FETs, which can be implemented in a lateral (with one or more lateral wires vertically stacked) or vertical configuration. The selected doping schemes and gate metals can also be powerful knobs to engineer the interface properties. In addition, specific steps for lateral NWFETs, such as the wires release process, will be addressed here. Vertical NWFETs, corresponding to the move from a 2D to a 3D CMOS layout, have the potential for lower parasitics, reduced power consumption and for enabling smaller, higher performing SRAM bitcells. We will present here alternative, novel approaches for building and characterizing these devices, focusing on channel-first schemes with improved process control, while tackling critical etch-layout dependences.

Published
2017
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