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1. Demonstration of SA TG Coplanar IGZO TFTs With Large Subthreshold Swing Using the Back-Gate Biasing Technique for AMOLED Applications

2. Electrical Performance and Stability Improvement of p-Channel SnO Thin-Film Transistors Using Atomic-Layer-Deposited Al₂O₃ Capping Layer

3. Development of high temperature operation silicon based MOSFET for harsh environment application

4. Quadratic symmetry of modified q-Euler polynomials

5. Degenerate Changhee-Genocchi numbers and polynomials

6. Effects of Capping Layers with Different Metals on Electrical Performance and Stability of p-Channel SnO Thin-Film Transistors

7. On Carlitz’s Type Modified Degenerate q-Changhee Polynomials and Numbers

26. 22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.

32. Effects of solution processable CuI thin films with Al2O3-based sandwiched architecture for high-performance p-type transistor applications.

34. A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.

38. Observations for the Ionosphere Using European Incoherent Scatter (EISCAT) in the Dayside Polar Cap/Cusp and Auroral Region

40. Sequential hypothermic and normothermic perfusion preservation and transplantation of expanded criteria donor livers

42. AN ANALYSIS OF THE INITIAL PRESALE RATE IN HOUSING PROJECTS USING A REGIME-SWITCHING MODEL

46. Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM.

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