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This paper presents a number of case studies in which various methods and tools are used to localize resistive open defects, including two-terminal IV, two-terminal electron-beam absorbed current (EBAC), electron beam induced resistance change (EBIRCH), pulsed IV, capacitance-voltage (CV) measurements, and scanning capacitance microscopy (SCM). It also reviews the advantages and limitations of each technique.

With the 3D stack-die technology, top die and base die are stacked together with micro-bumps for die-to-die interconnection and a through silicon via (TSV) for die-to-package connection. This technology provides tremendous flexibility as designers seek to "mix and match" technology IP blocks with various memory and I/O elements in novel device form factors. Even though the lock-in thermal detection technique had been demonstrated as a useful debug technique to detect defects on packages or pin related fails on 3D stack-die configuration, it is difficult to apply this technique to do functional debug. This paper presents a novel base die debug technique with TSV wirebond for 3D stack-die devices. A comprehensive study on the base die debug flow with real failing cases is also presented. Base die debug techniques will need to continue to be innovated to provide complete debug solutions for such platform.

On older semiconductor technology, electron-beam probing (EBP) for active voltage contrast and waveform on frontside metal lines was widely utilized. EBP is also being extended to include the well-known optical techniques such as signal mapping imaging (SMI) with the use of a lock-in amplifier in the signal chain and e-beam device perturbation. This paper highlights some of the achievements from an Intel in-house built e-beam tool on current technology nodes. The discussion covers the demonstration of fin and contact resolution on the current technology nodes by EBP and the analysis of the SRAM array with EBP and EBP of metal lines. By utilizing EBP, it has been demonstrated that logic state imaging, SMI, and waveform have significantly improved spatial resolution compared to the current optical fault isolation analogues.

This paper shows for the first time chip level electron beam probing on fully functional 10nm and 14nm node FinFET chips with sub-fin level resolution using techniques developed in house. Three novel electron beam probing techniques were developed and used in the debug and fault isolation of advanced node semiconductor devices. These techniques were E-beam logic state imaging, electron-beam signal image mapping, and E-beam device perturbation. Two tools that can offer all three techniques were constructed and used in production. The techniques have been successfully applied to real case chip debug and fault isolation on advanced 10nm and 14nm FinFET on production tools developed in-house. Sub-fin level resolution was achieved for the first time.

Methods to integrate different crystal orientations, strain states, and compositions of semiconductors in planar and preferably flexible configurations may enable nontraditional sensing-, stimulating-, or communication-device applications. We combine crystalline-silicon nanomembranes, patterning, membrane transfer, and epitaxial growth to demonstrate planar arrays of different orientations and strain states of Si in a single membrane, which is then readily transferable to other substrates, including flexible supports. As examples, regions of Si(001) and Si(110) or strained Si(110) are combined to form a multicomponent, single substrate with high-quality narrow interfaces. We perform extensive structural characterization of all interfaces and measure charge-carrier mobilities in different regions of a 2D quilt. The method is readily extendable to include varying compositions or different classes of materials.

We present both experimental results and a compact model on nanoscale thermal transport in the vicinity of a hot spot in silicon. Effective-local-temperature measurements on the nanoscale are influenced by localized heating effect and a thermal interface resistance, as well as by the spreading resistance in silicon. Ballistic phonon transport is observed for nanoheaters where the interface thermal resistance contribution can be minimized. Thermoelectricity in silicon nanostructures is investigated as a possible route to convert thermal energy into electricity.

A novel fault isolation technique, electron beam induced resistance change (EBIRCh), allows for the direct stimulation and localization of eBeam current sensitive defects with resolution of approximately 100nm square, continuing a history of beam based failure isolation methods. EBIRCh has been shown to work over a range of defects, significantly decreasing the time required for isolation of shorts through straightforward high resolution imagery, allowing for explicit visual defect isolation with a linear resolution of approximately 10nm. This paper discusses the operational setups for the source and amplifier while performing an EBIRCh scan, describes the processes involved in the Intel test vehicle that was used to test EBIRCh, and provides information on two independent functional theories for EBIRCh that operate in conjunction to a greater or lesser extent depending on the defect type. EBIRCh is expected to improve through-put and resolution on various defect types compared to conventional fault isolation techniques.

In order to increase the failure temperature of Ta diffusion barrier for Cu, we investigated the effect of a thin V insertion layer (100 A) into Ta film with/without ion bombardment on Ta diffusion barrier performance in Cu metallization. When the Ta/V/Ta diffusion barrier was deposited without concurrent ion bombardment, the insertion of the thin V layer into Ta film was not effective to improve the barrier performance of Ta film, because of the thermal instability of the Ta/V/Ta multilayer caused by the reaction between the Ta/V/Ta films and Si substrate. Meanwhile, when the Ta/V/Ta diffusion barrier was deposited with ion bombardment, the insertion of the thin V layer into Ta film improved barrier properties significantly. This was attributed not only to the densification of grain boundaries in Ta/V/Ta films, but also to the formation of two thermally stable sharp interfaces between Ta and V by ion bombardment, resulting in the reduction of the fast diffusion of Cu through Ta/V/Ta films.

We report thermoelectric measurements on a silicon nanoribbon in which an integrated gate provides strong carrier confinement and enables tunability of the carrier density over a wide range. We find a significantly enhanced thermoelectric power factor that can be understood by considering its behavior as a function of carrier density. We identify the underlying mechanisms for the power factor in the nanoribbon, which include quantum confinement, low scattering due to the absence of dopants, and, at low temperatures, a significant phonon-drag contribution. The measurements set a target for what may be achievable in ultrathin nanowires.

A scaling study of "localized heating effect" or ballistic phonon transport at cryogenic temperature in crystalline silicon is reported using electrical Joule heating and thermometry of patterned platinum nanoheaters. The thermal resistances of nanoheaters with width ranging from 100 nm up to 5000 nm were measured. The experimental results were processed and analyzed using a very simple thermal resistance model, which must be eventually improved and perfected using simultaneous three-dimensional electrical and heat transfer numerical simulations. However, the preliminary results revealed several important trends indicating the prevalence of localized heating or sub-continuum transport phenomena in the vicinity of a hotspot at low temperatures.

Ultra low power CMOS 6T-SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric were successfully demonstrated (bit-cell size=2.14 /spl mu/m/sup 2/). Equivalent oxide thickness (EOT) of 1.56 nm, the thin high-k gate dielectric NMOS and PMOS transistor had 470 and 150 /spl mu/A//spl mu/m at Ioff=0.1 nA//spl mu/m and Vdd=1.2 V, respectively. By deliberate optimizing the conditions of post nitridation and post deposition annealing (PDA) such as O/sub 2/ and N/sub 2/ PDA temperature, 60 and 82% of NMOS and PMOS mobility, respectively, compared to those of oxynitride were achieved without increasing EOT. And also, reliabilities of TDDB and HCI, and flicker noise characteristics of the thin high-k transistors were improved. For the 6T-SRAM with optimized thin high-k gate dielectric, static noise margin (SNM), cell delay, and chip yield were comparable to those of the oxynitride device while dynamic power was more than 2 orders lower (Vdd=1.0/spl sim/1.2 V).

Ultra low power 1.10 /spl mu/m/sup 2/ 6T-SRAM chip with HfO/sub 2/-Al/sub 2/O/sub 3/ gate dielectric was for the first time successfully demonstrated for the system-on-chip applications. By carefully optimizing gate pre-doping process, gate leakage current was dramatically suppressed and poly deletion was reduced. Device performance was improved by 15% and 12% for NFET and PFET, respectively. The threshold voltage of long channel transistor was well controlled to the acceptable value (0.4V) by channel engineering. Equivalent oxide thickness of HfO/sub 2/-Al/sub 2/O/sub 3/ film was 17/spl Aring/ and gate leakage current density was 1600-times lower than that of the oxynitride. Current performance of 90nm gate length NFET and PFET with HfO/sub 2/-Al/sub 2/O/sub 3/ were 335 and 115 /spl mu/A/ /spl mu/m, while Ioff were 0.9 and 2.0pA/ /spl mu/m, respectively. SNM value of 1.10 /spl mu/m/sup 2/ 6T-SRAM bit cell was 340mV at Vdd = 1.2V. Stand-by current of the SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ was decreased by 2 orders, while access time was 1.65 times larger compared with that of SRAM chips with oxynitride at Vdd = 1.2V.

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1 mA/cm/sup 2/ at V/sub g/=+1.0 V) and low EOT (15.6 /spl Aring/) sufficiently satisfy the specifications (EOT=12/spl sim/20 /spl Aring/, J/sub g/=2.2 mA/cm/sup 2/) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2 V V/sub dd/ are 585 /spl mu//spl Aring///spl mu/m (I/sub off/= 10 nA//spl mu/m) for nMOSFET and 265 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET, which are approximately 80% of those of nitrided SiO/sub 2/. In terms of I/sub on/-I/sub off/ characteristics of n/pMOSFETs, these results represent the best current performance compared with previous reports for poly-Si gate CMOSFETs with high-k gate dielectrics.