Search

Chirp-sequence-based Frequency Modulation Continuous Wave (FMCW) radar is effective at detecting range and velocity of a target. However, the target detection algorithm is based on two-dimensional Fast Fourier Transform, which uses a great deal of data over several PRIs (Pulse Repetition Intervals). In particular, if the multiple-receive channel is employed to estimate the angle position of a target; even more computational complexity is required. In this paper, we report on how a newly developed signal processing module is implemented in the FPGA, and on its performance measured under test conditions. Moreover, we have presented results from analysis of the use of hardware resources and processing times.

When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann`t fully improve performance because a target device doesn`t know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don`t know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about .