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Your search keyword '"I. Demonie"' showing total 3 results
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3 results on '"I. Demonie"'

1. Supervia Process Integration and Reliability Compared to Stacked Vias Using Barrierless Ruthenium

Author

Zaid El-Mekki, F. Schleicher, Frederic Lazzarino, D. Trivkovic, Zsolt Tokei, B. De-Wachter, S. V. Gompel, L. Halipre, E. Vancoille, S. Decoster, G. Muroch, Thomas Witters, L. Dupas, O. Varela-Pereira, B. Briggs, Quoc Toan Le, Harinarayanan Puliyalil, Christopher J. Wilson, Philippe Leray, N. Jourdan, I. Demonie, C. Lorant, Joost Bekaert, Nancy Heylen, Y. Kimura, Rogier Baert, M. H. van der Veen, J. Versluijs, Miroslav Cupak, Patrick Verdonck, K. Croes, Manoj Jaysankar, Anne-Laure Charley, J. Heijlen, J. Uk-Lee, Ivan Ciofi, Y. Drissi, V. Vega-Gonzalez, S. Paolillo, H. Vats, D. Montero, L. Rynders, Els Kesters, M. Ercken, A. Lesniewska, R. Kim, Lieve Teugels, and T. Webers

Subjects
Thermal shock, Reliability (semiconductor), Materials science, chemistry, Process integration, Analytical chemistry, chemistry.chemical_element, Time-dependent gate oxide breakdown, Dielectric, Tin, Ruthenium
Abstract

The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with respect to the stacked-via configuration. SV first and SV last integration approaches were electrically tested using full barrierless ruthenium (Ru) on a dielectric low-k 3.0. A maximum AR = 3.8 was achieved with ~2.4 times lower resistance than the alternative stacked-via configuration. Thermal shock tests produced no SV failure after 1000 cycles between -50 °C and 125 °C, and 250 hours. Time-dependent-dielectric-breakdown (TDDB) tests between SV and M2 lines gave a TTF 63.2% (at 1 MV/cm) > 10 years, when 3 M2 tracks are blocked.

Published
2020
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2. Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

Author

P. Morin, Julien Ryckaert, Doyoung Jang, Lieve Teugels, Efrain Altamirano-Sanchez, M. H. Na, Jürgen Bömmels, F. Schleicher, S. Wang, A. Sepúlveda, Serge Biesemans, C. Lorant, I. Demonie, Gayle Murdoch, E. Dentoni Litta, A. Lesniewska, Zsolt Tokei, Bilal Chehab, Farid Sebaai, Antony Premkumar Peter, N. Nagesh, Naoto Horiguchi, Frederic Lazzarino, Boon Teik Chan, Geert Hellings, O. Varela Pedreira, N. Jourdan, D. Radisic, O. Richard, Z. Tao, Hans Mertens, P. Marien, Anshul Gupta, Nancy Heylen, Steven Demuynck, and Katia Devriendt

Subjects
Materials science, business.industry, Annealing (metallurgy), chemistry.chemical_element, Dielectric, Electromigration, law.invention, Fin (extended surface), chemistry, law, Optoelectronics, Node (circuits), business, Tin, Spark plug, Scaling
Abstract

This paper reports BPR/Via-to-BPR (VBPR) module development at 24nm fin pitch (FP) / 42nm contacted gate pitch (CPP), and W and Ru-BPR and Ru- Contact-to-Active (M0A)/VBPR resistance (R) & electromigration (EM). BPR dielectric barrier, BPR plug barrier, and fin reveal are optimized to enable BPR scaling. A self-aligned VBPR etch is also demonstrated by Q-ALE process. Ru-BPR meets BPR line R target target 1100 h at 5 MA/cm2 at 330 °C.

Published
2020
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3. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

Author

N. Jourdan, Katia Devriendt, E. Dupuy, Hans Mertens, S. Paolillo, Guillaume Boccardi, F. Schleicher, E. Sanchez, Romain Ritzenthaler, Frank Holsteyns, Z. Tao, Sylvain Baudot, Sofie Mertens, Haroen Debruyn, Kevin Vandersmissen, Thomas Chiarella, P. Morin, Antony Premkumar Peter, Anshul Gupta, Erik Rosseel, Min-Soo Kim, Nouredine Rassoul, Boon Teik Chan, Christopher J. Wilson, D. Radisic, Lieve Teugels, A. De Keersgieter, D. Yakimets, I. Demonie, N. Bontemps, C. Drijbooms, Sujith Subramanian, Bilal Chehab, Paola Favia, C. Lorant, Farid Sebaai, Steven Demuynck, Frederic Lazzarino, E. Dentoni Litta, G. Mannaert, Houman Zahedmanesh, Yong Kong Siew, J. Cousserier, T. Hopf, B. Briggs, Manoj Jaysankar, Jerome Mitard, K. Kenis, A. Sepúlveda, S. Wang, Naoto Horiguchi, Goutham Arutchelvan, E. Capogreco, O. Varela Pedreira, D. Zhou, Jürgen Bömmels, and Zsolt Tokei

Subjects
010302 applied physics, Materials science, business.industry, chemistry.chemical_element, 02 engineering and technology, Tungsten, 021001 nanoscience & nanotechnology, 01 natural sciences, Electromigration, Cmos scaling, CMOS, chemistry, Booster (electric power), Logic gate, 0103 physical sciences, Optoelectronics, 0210 nano-technology, business, Low resistance, Scaling
Abstract

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

Published
2020
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