Search

In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma () analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5pF to 6.5pF with a worst case PSRR of 0.5% from 0.3V to 0.42V (0.67% from 0.3V to 0.6V). With a 3.5pF input capacitance and a 0.3V supply, the stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2fF/LSB) with a conversion frequency of 371Hz. With an average power consumption of 40nW and a sampling frequency of 47.5kHz, a figure-of-merit (FoM) of 0.78pJ/conv-step is achieved. [ABSTRACT FROM AUTHOR]

Healthcare electronics count on the effectiveness of the on-patient signal preprocessing unit to moderate the wireless data transfer for better power efficiency. In order to reduce the system power in long-time ECG acquisition, this work describes an on-patient QRS detection processor for arrhythmia monitoring. It extracts the concerned ECG part, i.e., the RR-interval between the QRS complex for evaluating the heart rate variability. The processor is structured by a scale-3 quadratic spline wavelet transform followed by a maxima modulus recognition stage. The former is implemented via a symmetric FIR filter, whereas the latter includes a number of feature extraction steps: zero-crossing detection, peak (zero-derivative) detection, threshold adjustment and two finite state machines for executing the decision rules. Fabricated in 0.35-\mum CMOS the 300-Hz processor draws only 0.83 \,\mu W , which is favorably comparable with the prior arts. In the system tests, the input data is placed via an on-chip 10-bit SAR analog-to-digital converter, while the output data is emitted via an off-the-shelf wireless transmitter (TI CC2500) that is configurable by the processor for different data transmission modes: 1) QRS detection result, 2) raw ECG data or 3) both. Validated with all recordings from the MIT-BIH arrhythmia database, 99.31% sensitivity and 99.70% predictivity are achieved. Mode 1 with solely the result of QRS detection exhibits 6\,\times reduction of system power over modes 2 and 3. [ABSTRACT FROM PUBLISHER]

Portable/Implantable biomedical applications usually exhibit stringent power budgets for prolonging battery life time, but loose operating frequency requirements due to small bio-signal bandwidths, typically below a few kHz. The use of sub-threshold digital circuits is ideal in such scenario to achieve optimized power/speed tradeoffs. This paper discusses the design of a sub-threshold standard cell library using a standard 0.18-µm CMOS technology. A complete library of 56 standard cells is designed and the methodology is ensured through schematic design, transistor width scaling and layout design, as well as timing, power and functionality characterization. Performance comparison between our sub-threshold standard cell library and a commercial standard cell library using a 5-stage ring oscillator and an ECG designated FIR filter is performed. Simulation results show that our library achieves a total power saving of 95.62% and a leakage power reduction of 97.54% when compared with the same design implemented by the commercial standard cell library (SCL).

Healthcare electronics count on the effectiveness of the on-patient signal preprocessing unit to moderate the wireless data transfer for better power efficiency. In order to reduce the system power in long-time ECG acquisition, this work describes an on-patient QRS detection processor for arrhythmia monitoring. It extracts the concerned ECG part, i.e., the RR-interval between the QRS complex for evaluating the heart rate variability. The processor is structured by a scale-3 quadratic spline wavelet transform followed by a maxima modulus recognition stage. The former is implemented via a symmetric FIR filter, whereas the latter includes a number of feature extraction steps: zero-crossing detection, peak (zero-derivative) detection, threshold adjustment and two finite state machines for executing the decision rules. Fabricated in 0.35-μm CMOS the 300-Hz processor draws only 0.83 μW, which is favorably comparable with the prior arts. In the system tests, the input data is placed via an on-chip 10-bit SAR analog-to-digital converter, while the output data is emitted via an off-the-shelf wireless transmitter (TI CC2500) that is configurable by the processor for different data transmission modes: 1) QRS detection result, 2) raw ECG data or 3) both. Validated with all recordings from the MIT-BIH arrhythmia database, 99.31% sensitivity and 99.70% predictivity are achieved. Mode 1 with solely the result of QRS detection exhibits 6× reduction of system power over modes 2 and 3.

In recent years, algorithm based on Mathematical Morphology and wavelet transform has been proposed for ECG QRS Complex detection. However, its intensity of computation is high. This paper proposes the algorithm and hardware architecture for the whole system of QRS Complex detection based on Mathematical Morphology and Quadratic Spline wavelet transform, with implementation in Field Programmable Gate Array (FPGA). The system consists of Morphological filtering, Quadratic Spline wavelet transform and Modulus Maxima Pair Recognition modules. The parallel and pipelined architecture of system can operate in the maximum 35MHz with throughput of one sample per clock cycle. The QRS Complex detection accuracy for MIT/BIH arrhythmia database recordings and resource consumption are reported. The design is suitable for both batch processing of huge volume ECG data and real time applications for portable devices.