144 results on '"Imai, Masaharu"'
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2. RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
3. MeSOC-I A Mixed Signal SOC for Bioinstrumentation in Medical Treatment and Healthcare System
4. Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model
5. A Code Selection Method for SIMD Processors with PACK Instructions
6. Compiler Generation Techniques for Embedded Processors and their Application to HW/SW Codesign
7. Electronic triage system for continuously monitoring casualties at disaster scenes
8. A MEMS electromagnetic optical scanner for a commercial confocal laser scanning microscope
9. ASIP Meister
10. Verification Challenges in Configurable Processor Design with ASIP Meister
11. A Code Selection Method for SIMD Processors with PACK Instructions
12. Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation
13. Flexible sensor sheet for real-time pressure monitoring in artificial knee joint during total knee arthroplasty
14. A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems
15. Deformable Part Model Based Arrhythmia Detection Using Time Domain Features
16. Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface
17. A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis
18. 日本語・日本文化学類の国際交流 （＜特集＞「現場から（１）学群・学類教育」）
19. 日本文化史教育の重要性 （＜特集＞教育の社会対応＞）
20. A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems
21. Cortical neural excitations in rats in vivo with using a prototype of a wireless multi-channel microstimulation system
22. Preliminary study of a new home healthcare monitoring to prevent the recurrence of stroke
23. An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC
24. Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model
25. An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology
26. A New Available Bandwidth Estimation Method Using RTT for a Bottleneck Link
27. An efficient lossless data compression method based on exponential-Golomb coding for biomedical information and its implementation using ASIP technology
28. An AMBA hierarchical shared bus architecture design space exploration method considering pipeline, burst and split transaction
29. Chapter 7 - ASIP Meister
30. 日本文化史教育の重要性 （＜特集＞教育の社会対応＞）
31. A framework for remote monitoring of early heart attack diagnosis system for ambulatory patient.
32. Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion
33. On-chip Communication Buffer Architecture Optimization Considering Bus Width
34. Electronic triage system for continuously monitoring casualties at disaster scenes
35. A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring
36. Automated architecture exploration for low energy reconfigurable AGU
37. Electronic Triage System: Casualties Monitoring System in the Disaster Scene
38. A Person with Hobby
39. Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design
40. Biological information sensing technologies for medical, health care, and wellness applications
41. Generation of application-domain Specific Instruction-set Processors
42. Two-stage configurable decoder model for multiple forward error correction standards
43. Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm
44. Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)
45. Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors
46. A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions
47. A new compilation technique for SIMD code generation across basic block boundaries
48. Optimization method for scheduling length and the number of processors on multiprocessor systems
49. Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors
50. Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor
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