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T-type three-level inverters have attracted extensive attention for their utility in many applications, especially photovoltaic power generation. For these inverters, parallel operation offers superior performance in efficiency, reliability, and scalability. However, the introduced circulating current (CC) may cause overcurrent in line, which seriously threatens the safety and stability of the system. The mechanism of CC lacks detailed analysis in single-phase modular inverters. Thus, an accurate mathematical model is established and a CC suppression method is proposed in this paper for parallel-operated single-phase T-type three-level inverters. Firstly, the characteristics of port degradation are analyzed, and an improved equivalent circuit is introduced based on the findings. Then, according to the improved equivalent circuit, a detailed mathematical model is established. Using this model, excitation sources of CC are analyzed and divided into three parts. After that, a CC suppression method involving carrier-based pulse width modulation with offset voltage injection is proposed, and a deadbeat controller is designed to calculate the offset voltage. Moreover, the proposed method can balance the neutral point voltage across DC-link capacitors as well. Simulation and experimental results validate the theoretical analysis and effectiveness of the proposed scheme.

The dual neural network-based k-winner-take-all (DNN-kWTA) is an analog neural model that is used to identify the k largest numbers from n inputs. Since threshold logic units (TLUs) are key elements in the model, offset voltage drifts in TLUs may affect the operational correctness of a DNN-kWTA network. Previous studies assume that drifts in TLUs follow some particular distributions. This brief considers that only the drift range, given by [-Δ, Δ], is available. We consider two drift cases: time-invariant and time-varying. For the time-invariant case, we show that the state of a DNN-kWTA network converges. The sufficient condition to make a network with the correct operation is given. Furthermore, for uniformly distributed inputs, we prove that the probability that a DNN-kWTA network operates properly is greater than (1-2Δ)ⁿ. The aforementioned results are generalized for the time-varying case. In addition, for the time-invariant case, we derive a method to compute the exact convergence time for a given data set. For uniformly distributed inputs, we further derive the mean and variance of the convergence time. The convergence time results give us an idea about the operational speed of the DNN-kWTA model. Finally, simulation experiments have been conducted to validate those theoretical results.

Vienna rectifier is widely employed in the electric vehicle charging system and wind turbine system due to its higher efficiency and lower total harmonic distortion. However, the Vienna rectifier with the LCL filter has the challenge of resonant current mitigation, current zero-crossing distortion elimination, neutral point (NP) voltage balance and switching loss reduction. Moreover, these problems are mutually coupled. To overcome these issues, the causes of resonant current with the conventional discontinuous pulsewidth modulation (PWM) (DPWM) method is analyzed, which reveals that the abrupt change of reference voltage has a wide range harmonics band and easily induces the resonant current at resonant frequency. Then, based on the analysis, a novel three-layer DPWM method with three offset voltages injection is proposed. In the first layer, the NP voltage balance is realized by injecting the first offset voltage. In the second layer, the second offset voltage, which makes the discontinuous reference voltages smooth is presented to reduce the losses and suppress the resonant current. In the third layer, the third offset voltage is elaborated to eliminate current zero-crossing distortion caused by different power factor and the LCL filter. Based on the proposed method, resonant current mitigation, current zero-crossing distortion elimination, NP voltage balance are realized simultaneously with reduced switching losses. The effectiveness and performance of the proposed method are verified by simulation and experiment.

In this paper, fault diagnosis and tolerant control methods are proposed for an open-switch fault in a Vienna rectifier. The proposed diagnosis method uses only the input currents to detect an open-switch fault without any additional hardware. In the proposed tolerant control, the offset voltage is used to restore the input currents when an open-switch fault occurs in a Vienna rectifier. In addition, the proposed tolerant control considers the balance of the neutral-point voltage. This method can improve the total harmonic distortion of the current and mitigate the DC-link voltage ripple. The effectiveness of the proposed open-switch fault diagnosis and tolerant control method is verified by simulated and experimental results.

The charge-generating sensors are widely used in many applications in consumer, automotive and medical electronics. They generate a charge proportional to the applied input quantity: pressure, temperature, acceleration, strain, light, etc. Usually, charge amplifiers are used to register such signals. The charge amplifier is an integrator that integrates the input current over time. In continuous-time signal processing, a parallel resistor is used to dissipate the energy stored on the integration capacitor, and such self-zeroed integrator circuits are known as lossy integrators. To achieve low-frequency operation, when a capacitor is in the picofarad range, a very high-ohmic resistor, in the range of gigaohms, must be used. Such a high-ohmic resistor increases the output offset voltage to an unacceptable level. To overcome the output offset problems, a composite charge amplifier has been recently introduced. This paper presents an innovative lossy integrator readout circuit which contains only one opamp in the feedback. The circuit can be easily adapted to the needed gain and cut-off frequency. Its operation is validated by experimental results. The sufficiently low high-pass cut-off frequency allows the circuit to be used for biosignal amplification. Heart and respiration rates can be easily recorded with piezoelectric sensors attached to the wrist or lung wall. The presented circuit can benefit many applications where charge-to-voltage conversion is needed.

Four-switch three-phase inverters (FSTPIs) are generally applied as fault-tolerant topologies or cost-effective topologies for induction motor (IM) drives. However, conventional predictive torque control (PTC) for FSTPI-fed IM suffers from poor steady-state performance and tedious weighting factor assignment. In this article, a PTC based on discrete space vector modulation (PTC-DSVM) for an FSTPI-fed IM drive is proposed. First, the relationship between the dc-link capacitor voltage offset (CVO) and the load current is derived, and a stator voltage compensation strategy is proposed to suppress the CVO. Meanwhile, a reference-voltage-vector-error-based cost function that combines the reference stator flux vector control, the stator voltage compensation strategy, and the deadbeat control is designed to fully eliminate the weighting factors in the cost function of the conventional PTC. In addition, a DSVM scheme is developed to increase the number of admissible voltage vectors and improve the steady-state performance of IM drives. A preselection algorithm based on the offset voltage vector and sector division is designed to reduce the number of candidate voltage vectors. Extensive simulations and experimental results with a 2.2-kW IM are demonstrated to validate the effectiveness of the proposed control strategy.

Modulation schemes play a key role in effectively driving the current source converter (CSC). Among various modulation schemes, the carrier-based pulse width modulation (CB-PWM) has gained much attention owing to its inherent auto-sequencing process. However, the fixed switching patterns in the existing CB-PWM methods reduce the available degrees of freedom, which imposes underlying restrictions on the performance of a CSC (e.g., to minimize the switching frequency or to reduce the current ripple). To address this issue, an innovative concept of two-stage modulation, which modulates the active and zero current vectors in a switching sequence, respectively, in two stages, is explored in this article. Based on that, this article proposes a generic CB-PWM scheme with adjustable switching patterns for flexibly modulating the CSC. Its mechanism is presented to develop its modulation characteristics. It shows that the proposed PWM scheme can flexibly achieve different modulation objectives by only adjusting the offset voltage in the second stage. Three derivations of the proposed scheme have then been discussed in detail, which can achieve a minimized switching frequency, a reduced dc-link current ripple, or a compromise between them. Representative experimental results have been provided to verify the effectiveness of the proposed modulation scheme.

In this paper, passive-less fully-digital operational transconductance amplifiers (DIGOTA) for energy- and area-constrained systems are modeled and analyzed from a design viewpoint. The digital behavior of DIGOTAs is modeled as an equivalent small-signal differential-mode circuit with zero bias current, and a common-mode feedback loop operating as a self-oscillating threshold sampler. Such continuous-time equivalent circuits are used to derive an explicit model of the main performance parameters that are generally adopted to characterize OTAs. This provides an insight into circuit operation and allows to derive practical guidelines to achieve a given design target. Among the others, an explicit model is derived for the DC gain, the frequency response, the gain-bandwidth product, the input-referred noise, and the input offset voltage. The models are validated via direct comparison with multi-die measurement results in CMOS 180 nm. From an application viewpoint, the voltage (power) reduction down to 0.25 V (sub-nW) uniquely enable direct harvesting (e.g., with solar cells), suppressing any intermediate DC-DC conversion stage. This further enhances the area efficiency advantage of DIGOTA stemming from its fully-digital nature, making it well suited for cost-sensitive and purely-harvested systems.

Sensor integration is widely demanded in many applications. For sensor fabrications, a cross-point structure is beneficial because of its low cost, while the readout interface circuit suffers from sneak currents, which can lead to enormous readout error. In this study, the developing electric olfaction system which integrates over 1,000 gas sensors was introduced. Compared to previous works, the array size tends to become large, and resistance values can be widely distributed. We employed the conventional voltage feedback method for the interface circuit because it can measure a wide range of resistance. However, since it constitutes the voltage divider circuit with the selected resistor and the reference resistance by an op-amp unity gain feedback, the readout accuracy is affected by its large load sensor resistance. Therefore, a calibration technique for the voltage feedback method was proposed. The feedback error caused by the load resistance and op-amp nonidealities was analyzed with a simplified circuit, in which circuit parameters such as an array scale, a reference resistance, and an op-amp output impedance were variable. The sneak currents were estimated in the calibration by utilizing the op-amp input difference, and their effects were eliminated. The simulation results showed that the readout error of $32\times 32$ resistive array with 10% distributed resistance could be decreased from around 3% to less than 0.005%. The dependency of the readout accuracy on an op-amp’s gain input offset voltage was evaluated systematically to apply the calibration to a practical system.

Memory, speed, reliability, and efficiency are the main characteristics of concern in new contemporary control techniques of electric power converters. Space vector pulse width modulation (SVPWM) is a widespread digital compute-intensive control technique used in the control of power converters. This study aims to overcome the large number of calculations needed by the SVPWM algorithm, which limits its implementation in many advanced industrial applications. This paper presents a low-cost software implemented simplified SVPWM technique. The proposed strategy generates the inverter switching times in a straightforward manner with no need for complicated and time-consuming sector identification and look-up switching tables. A simulation study has been done using MATLAB/SIMULINK environment for the three-phase voltage source converter (VSC). The results in terms of total harmonic distortion (THD) in the converter line voltage are compared for the proposed technique, conventional SVPWM, and space pulse width modulation (SPWM). The execution time is reduced considerably with a slight increase in the value of THD and about 14.4 percent DC-link voltage utilization over the SPWM.

The infrared detector (or IR detector) is an optoelectronic component and represents the core element of gas analyzers, flame sensors, devices of spectral analysis, as well as non-contact temperature measurement. pyroelectric infrared detectors work with stabilization time in a wide operating temperature range (-55 ... 85) °C, capable of measuring the slightest amounts of infrared radiation (as little as a fraction of a nW) with wavelengths between 1 µm and > 25 µm. The difference of the good pyroelectric or No good (NG) devices shown by graph of voltage offset operating that can check by manual using Digital Multi Meter or semi auto by using microcontroller One of importance measuring of IRD sensors is Offset Voltage, stabilization of offset voltage indicate the sensor is stable with certain level value. Stabilization value measurement during measuring time means the average value not so much different with fluctuation value. 10 bit ADC on Atmega 328 that main microcontroller on Arduino Uno is capable to measure the Offset Voltage of IRD sensor and check the measurement values is within specification of IRD sensor.

Structured arrays and master slice arrays are often used to reduce cost, design and test time for radiation hardened analog integrated circuits. One of such master slice arrays is МН2ХА030, which uses bipolar and junction field-effect transistors. The purpose of this article is to estimate the effect of ionizing radiation on the parameters of the operational amplifier OAmp2 and comparators ADComp1 and ADComp3 created on the МН2ХА030 master slice array. Еhe results of measurements of analog components after exposure to 60Co gamma quanta with an absorbed dose of up to 700 krad and a fast electron fluence of up to 2.9·1015 el./cm2 with an energy of 6 MeV are presented. The OAmp2 operational amplifier provides a satisfactory level of basic static parameters (input current, offset voltage, voltage gain) at a fast electron fluence of up to 3.7·1014 el./cm2 with an energy of 6 MeV. There are a decrease in the voltage gain and an increase in the offset voltage at electron fluence of greater than 1015 el./cm2. The latter can be caused by a decrease in the efficiency of the common-mode signal feedback integrated into operational amplifier with a significant drop in current gain of bipolar transistors. All considered analog components provide a satisfactory level of basic static parameters at a fast electron fluence of up to 3.7·1014 el./cm2 with an energy of 6 MeV and an absorbed dose of 60Co gamma quanta of at least 700 krad. It is assumed that resistance of OAmp2, ADComp1, ADComp3 to the action of 60Co gamma quanta is significantly higher and requires further research. The developed analog components can be used in signal reading devices required in front-end of sensors for space instrumentation and nuclear electronics.

Essential design requirements for a sense amplifier (SA) used in the resistance monitoring write termination (RM-WT) scheme are suggested to reduce the write energy of spin-transfer-torque random access memory (STT-RAM) while achieving a write pass yield comparable to that of a conventional write operation. In addition, a self-referenced single-ended RM-WT (SS-RM-WT) scheme is proposed. To reduce the offset voltage, a single-ended sensing circuit (SE-SC) is used in the SA. A data-aware input voltage-transfer method is also adopted in the SE-SC to maximize the input voltage difference. By adopting a capacitor between the output of the SE-SC and the input of an inverter generating a logical output used for the write termination, the conflict between maintaining and changing the output of the SE-SC is resolved. The simulation results using the industry-compatible 65-nm technology HSPICE model parameters show that the proposed SS-RM-WT scheme achieves a 44% write energy saving on average without increasing the write error rate. Area overhead is only 11.8% for a 256-kb STT-RAM array, whereas that of the previous self-referenced RM-WT schemes is up to 42.5%.

Electrohydrodynamic (EHD) printing is a novel printing technology with high printing resolution, making it suitable for applications such as tissue engineering and micro/nanomanufacturing. Inkjets from EHD fall on the substrate either in the continuous or drop-on-demand (D-O-D) mode. In this research, the D-O-D-based EHD printing process was used to print micro droplets of bioink assisted by a pulse electric field. A 2% (g/mL) sodium alginate solution was used as the bioink. A general full factorial design was used to analyze and observe the relation between the bioink droplet quality and the EHD process parameters. The diameter of the droplet, droplet generation rate, distance between two droplets, and the droplet consistency are the four major responses to evaluate the printing quality. The EHD process parameters, offset voltage, pulse width, and frequency, are the three regressor variables. After conducting the data analysis, it is observed that the higher frequency and the lower voltage produced the smaller droplet diameter, higher droplet generation rate, and nearer distance among the droplets. However, this increased the variance in the droplet patterns thus reducing the consistency of the printing process. It was also found that pulse width had marginal significance on the quality of printed drops. From the data analysis, four regression models were developed to aid in finding the parameter combinations to print 2% sodium alginate at a desired droplet diameter, droplet generation rate, and droplet distance. This proposed model can be used as a guideline for EHD bioprinting experimental setup, and it will significantly reduce the efforts to determine the optimal process parameters.

When permanent magnet synchronous motors (PMSM) are used in pump and fan applications where no excessive performance is required, the V/f scalar control method can be applied to enhance the ease of use for end users. For the voltage reference generation in V/f control, existing methods requires motor parameters such as the stator resistance, inductance, and back EMF constant of the permanent magnet, which is identified before or during operation. However, this paper proposes a simple and convenient V/f control method that utilizes the motor parameters given on the name plate. In the proposed method, stable operations are ensured for the rated speed and load ranges without position sensors. For successful starting operation, a DC current control loop is included to calculate the initial offset voltage reference for the V/f pattern. The stability and effectiveness of the proposed method are analyzed and verified by MATLAB/Simulink and 3.7 kW IPM motor drive experiments.

To reduce the circuit area and support a 10-bit fully nonlinear gamma correction, a new column driver architecture constructed with a 10-bit one-stage low-voltage resistor string digital-to-analog converter (RDAC) (LVDAC) and a switched-capacitor amplifier (SC-AMP) is proposed. Because the LVDAC is implemented with low-voltage (LV) MOSFETs instead of high-voltage (HV) MOSFETs, the circuit area is drastically reduced. In addition, there is no need to use level shifters that must be used in the traditional column driver between the LV logic circuit and the HV DAC, thus further decreasing the circuit area. By utilizing a one-stage DAC architecture, the effective bit resolution of nonlinear gamma correction can be increased compared with previous two-stage DACs, in which the output voltages of the coarse DAC are interpolated. The output voltage of LVDAC is amplified by SC-AMP to reach the requisite HV to drive the display panel. In designing the SC-AMP, the effects of non-idealities, such as random offset voltage, capacitance mismatch, parasitic capacitance, and switching error are quantitatively analyzed, and circuit techniques to suppress the effects are presented. The proposed column driver was fabricated using a 90-nm CMOS process. The circuit area of the proposed 10-bit column driver is only 69.0% of that of the conventional 8-bit column driver because the conventional 8-bit HV RDAC (HVDAC) using 5-V MOSFETs is replaced by the proposed 10-bit LVDAC using 1.2-V MOSFETs, along with the SC-AMP with a gain of four to support the 5-V output voltage range. The measurement results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.2/−0.18 and +0.42/−0.06 LSB, respectively, with an LSB voltage of 4.5 mV. The measured maximum deviation of voltage outputs (DVOs) between 50 channels is 7.9 mV.

Serious reliability concerns of Static Random Access Memories (SRAMs) in nanometer technologies are the increased process variations as well as the various aging mechanisms. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena are the main factors related to the aging reliability reduction. This degradation affects speed, operating voltages, memory cell noise margins and sense amplifier input offset voltage. Thus, it is imperative to develop design techniques for aging tolerance that will provide the ability to sense aging levels, predict upcoming failures in the memory and early react to retain the reliable operation. In this work, a circuit for the periodic aging monitoring in SRAM sense amplifiers and memory cells is presented.

With the continuous intelligentization of power systems, the demand for the integration of digital chips and sensor chips such as the Internet of Things is also increasing. A CMOS lineal magnetic Hall sensor front-end working in current mode with programmable gain stage is designed and implemented with SMIC 55 nm standard CMOS technology. By using a spinning-current technique, chopper technique, and digital calibration technique to eliminate the offset voltage and nonlinearity, this magnetic Hall sensor can be easily integrated into digital systems like SoCs. This work has already finished the circuit simulation and layout design, and all simulation indicators basically reach the expected value. The maximum gain of proposed sensor systems can be up to 33.9 dB. The total power is less than 4 mW. And the total area is less than 0.113 μm2. The magnetic Hall sensor can be easily integrated into chips such as the power Internet of Things to form a single-chip-level SoC design, which is mainly used in applications such as circuit breakers and electric energy measurement.

A ripple-based constant on-time (RBCOT) control scheme is excellent in achieving fast transient response during the load current step. However, it suffers from severe electromagnetic interference (EMI) noise and inherent output voltage offset problem. A monolithic ripple-based adaptive on-time (RBAOT)-controlled buck converter is presented to overcome both drawbacks while retaining the advantage of RBCOT. The on-time is adjusted adaptively by detecting the switching node voltage, and thereby ensuring a pseudofixed switching frequency in a steady state, regardless of the input, output voltage, and load current conditions. A correction voltage generated by a coefficient in a virtual inductor current (VIC) circuit is introduced to counteract the offset voltage and enhance the output accuracy. The proposed scheme is simple to implement and suitable for high-conversion ratio applications. Experimental results show that the switching frequency is centered at 1 MHz with less than 6% variation for an output of 5 V and inputs ranging from 8 to 18 V. The output offset voltage is reduced from 16 to 1 mV for an 18 to 1.05-V conversion. For a load current step of 1 A, the output can be settled within $6~\mu \text{s}$ and the undershoot and overshoot voltages are controlled to be within 20 mV.

Effects of a fully natural aging of MEMS accelerometers are evaluated with regard to changes in their performance. Two models of commercial dual-axis accelerometers (two pieces of ADXL 202E and 203 by Analog Devices Inc.) with analog outputs were tested over a period of about 10 and 4 years, respectively. A custom computer controlled test rig was used for performing relevant experimental studies, employing the gravitational acceleration as the reference source. A methodology of determining the proposed indicators of aging phenomena is presented and discussed. Changes of the offset voltage and the scale factor were observed and a way of evaluating the overall error due to combined influence of these two parameters is proposed. It was found out that the changes of the output voltage generated by the tested accelerometers were considerable, resulting in respective maximal errors of about 52 mg (2.6%) (ADXL 202E) or 20 mg (1%) (ADXL 203). Simple ways of reducing the effects of aging are proposed.

This study investigates the charge injection barrier at the phthalocyanine (H2Pc)/Pd using accumulated charge measurement (ACM). Because the hole injection barrier is relatively small, the voltage ...

This paper presents a resonance suppression method that reduces current oscillation incurred by the LCL-filtered grid-connected converter’s discontinuous PWM (DPWM). First, the cause of LCL resonance is analyzed with an aspect of frequency and time domain for DPWM scheme. Then, voltage references are manipulated to decrease the resonance problem. In the proposed method, pole voltage references at the edge of offset voltage are slightly adjusted to reduce the current oscillation. In addition, a perturb and observe (P&O) technique is adopted to search the magnitude of an edge voltage. Through the simulation and experimental tests, the current oscillation is dramatically reduced while keeping the advantages of DPWM scheme. The proposed method can minimize the switching frequency under the grid harmonics regulation.

As high-density SRAMs must be designed to ensure a substantially small failure rate, the accurate yield estimation with practically acceptable runtime of circuit simulations is highly challenging. Here, a read access yield estimation method for high-density static random access memory (SRAM) is proposed. Instead of performing SPICE runs for the entire SRAM circuit, the proposed method partitions the SRAM into three parts—the control signal generation circuit, bitcell array, and sense amplifier (SA)—that determine three key parameters: word-line to SA enable delay, bit-line voltage difference, and SA offset voltage. Subsequently, the proposed method derives the probability density of these key parameters from each of the three partitioned circuits. Here, different methods are applied to derive the probability of the key parameters, considering the respective characteristics of each circuit part and parameter. According to our experimental results, the proposed method can accelerate the yield estimation by 500– $3000\times $ , compared with the brute-force Monte Carlo simulation method, and 10– $100\times $ compared with the other state-of-art methods. In addition, the proposed method can accelerate the circuit optimization procedure accompanied by multiple circuit revisions, that is, the circuit revisions can be reflected with SPICE runs only for the revised circuit part, unlike the previous methods that require SPICE runs for the entire SRAM.

In this work, a CMOS Miller Operational Amplifier (OpAmp) with high immunity to electromagnetic interference (EMI) is proposed. The proposed OpAmp has unique features, such as compact power and low output offset voltage, when compared to the classical Miller OpAmp and the robust Miller OpAmp reported in the literature. The proposed compact Miller OpAmp has a reduced area, when compared to the robust Miller OpAmp. The output offset current modeling equations are derived for the proposed compact Miller OpAmp including the body effect and channel length modulation. The results are validated with simulations in the presence of a test EMI signal of 1 Vpp in 1.8 V, 0.18 $\mu$ m CMOS technology. The power consumption of the proposed compact Miller OpAmp with source degeneration resistance $R_S$ is 8% less and the area is 5.6% less than the robust Miller OpAmp with source degeneration resistance $R_S$ . The performance result shows that the maximum EMI-induced input offset voltage for the proposed compact Miller OpAmp with source degeneration resistance $R_S$ is 4.6 mV over a wide frequency range from 1 MHz to 1 GHz, which is lower when compared to the classical Miller OpAmp and the robust Miller OpAmp with source degeneration resistance $R_S$ .

In this study, a simple carrier-based pulse-width modulation (CBPWM) method is proposed for a three-phase three-level neutral-point-clamped converter with neutral-point (NP) balancing, which can be applied to three-phase three-wire (TPTW) and three-phase four-wire (TPFW) converter systems simultaneously. First, the effect of each switching state for the NP potential in TPTW and TPFW systems is analysed in detail, and a newly NP control strategy by reconstructing the switching state and adjusting the corresponding duration time is deduced for all operation conditions, it only needs to add the offset voltage to the modulation reference voltage to guarantee the NP balance and is easy to implement. Then, under all operating conditions, the mathematical model of NP current is derived and analysed to evaluate the low-frequency voltage oscillation in the NP. Finally, the effectiveness and feasibility of the proposed CBPWM strategy are verified by the experimental results based on a 12 kVA laboratory prototype.

Single-phase three-level T-type inverter (3LT $^2$ I) has revealed superior performances in many applications. However, it inevitably faces the challenge of high switching loss and imbalanced neutral-point voltage with conventional carrier based pulsewidth modulation (CBPWM). To address these issues, an improved CBPWM strategy with maximum offset voltage injection is proposed to reduce the switching loss and balance the neutral voltage simultaneously. Neutral-point voltage balance is maintained by selecting P-type or N-type switching sequence, which depends on the sign of offset voltage. Also, switching loss is mitigated by reducing the number of total switching commutation. First, the restriction of injected offset voltage is investigated and when the offset voltage is maximum, the switching commutation is reduced. Then, to further reduce the number of switching commutation, a new set of carrier signals are proposed to realize zero switching commutation between P-type and N-type switching sequences. After the analysis, the proposed modulation method also has better common-mode voltage restriction and faster response of neutral-point voltage balance. Simulation and experiment have been conducted to verify the theoretical analysis.

A charge balancing technique that is applicable to dual-edge current nerve stimulators is proposed herein, which is primarily directed to achieving charge balance by controlling discharge times. Compared to the charge balancing technique proposed in other papers, the number of single-cycle imbalanced charges is less than 15 pC. In order to reduce the amount of imbalanced charge, indirect shunt technology, leakage current compensation technology and offset voltage compensation technology was proposed in this paper to build up a synchronization system. To ensure that the neural stimulator can still be in charge balance after performing multiple stimulation cycles, a short pulse insertion technique is applied to the circuit. The circuit was designed based on the TSMC 180 nm process and verified its functionality under the Cadence platform.

In a three-phase multilevel cascaded inverter (MLCI), when a failed module is bypassed, the number of modules in each phase becomes unbalanced. Under this condition, a method to obtain a balanced three-phase output is to move the neutral point of the MLCI. The neutral-point shift (NS) method has attracted a great deal of attention since the output of the inverter has a relatively low harmonic distortion when compared to other fault-tolerant operation methods. To move the neutral point, an offset voltage of the fundamental frequency component is injected. If the injected offset voltage exceeds the available range of the offset voltage, overmodulation occurs. Then, the output of the inverter is distorted. In this paper, the overmodulation regions of the NS method are analyzed for the fault-tolerant operation in the three-phase MLCI. In addition, a modified NS method is proposed to compensate for the overmodulation region. Both simulation and experimental results in a two-by-three MLCI demonstrate the performance of the proposed method.

Random offset in amplifiers arises mainly due to random variations i.e. inherent mismatch in transistor parameters and greatly impacts its overall design specifications, especially in case of low frequency application. It must be minimized for high precision in the amplifier’s performance. A new approach for minimization of random offset voltage in amplifiers has been proposed through the use of swarm intelligence based optimization algorithms due to their derivative free nature and easy search mechanism. The approach involves firstly, modelling the random offset voltage due to mismatch between transistors parameters based on Pelgrom’s model and then minimizing the formulated model subjected to design constraints using swarm intelligence based algorithms. Two case studies are considered, firstly, a high swing Folded Cascode Operational Transconductance Amplifier (OTA) and secondly, a Recycling Folded Cascode (RFC) OTA. Comparative analysis have been performed by recording best, worst and mean data for 2500 function evaluations and also using statistical analysis such as Friedmann’s test and Mann–Whitney’s U test. The results indicate that the Hybrid Whale Particle Swarm Optimization (HWPSO) algorithm outperforms the other state of the art algorithms by giving a minimum random offset voltage of 7.2 mV and 1.452 mV with a mean rank of 1.55 and 1.75 for the 1st and 2nd case studies respectively. Validation of HWPSO results have been done by performing simulations and Monte Carlo Analysis for the two amplifiers in Cadence Virtuoso, which are found to be in close agreement with the algorithmic results.

In this brief a constant on–time (COT) buck converter with high efficiency and low offset voltage is presented. It was fabricated with a TSMC $0.18{\mu }\text{m}$ 1P6M CMOS process. An additional current feedback path (ACFP) technique was incorporated to avoid subharmonic oscillation of the converter without a large equivalent series resistance (ESR) capacitor, thus reducing the output voltage ripple. However, the ACFP causes an offset voltage on the converter’s output voltage dc level with loading changes. The proposed offset cancellation can remove the dc level from current sensor in ACFP. Hence, the offset voltage can be reduced through a proposed offset cancellation technique. The experimental results revealed that the offset voltage of the proposed converter is 8mV under a 0.1A to 1A loading changes. The converter’s maximum power efficiency is 93.4 %, and its output voltage ripple is less than 18mV.

Based on three groups of different offset voltages, a bandgap reference (BGR) and power-ON reset (POR) hybrid circuit is implemented in 65-nm CMOS. The BGR using amplifier offset voltage and current matching, and the POR using offset voltage comparison and loop settling feature, respectively, are proposed. This circuit, with low-quiescent current, not only generates a stable reference voltage independent of voltage and temperature variations, but also provides a high-robust supply-ramp-rate-tolerant power-ON/brown-out reset signal with a hysteretic window of 18–24 mV. Experimental results show that the circuit with line regulations (LNRs) of 2.63%–4.28%/V and temperature coefficients (TCs) of 22–32 ppm/°C across multiple chips has a power dissipation around $2.25~\mu \text{W}$ from a 1-V supply voltage. The circuit achieves a low noise density of 18.5 nV/ $\surd $ Hz at 100-Hz offset frequency and a good figure of merit (FoM) performance. With an active core area of 0.014 mm2, the circuit has fixed reset trip voltages under the supply ramp time of 0.4–100 ms.

This brief presents an untrimmed sub-1V CMOS bandgap reference (BGR) where a dynamic-biased error amplifier (EA) is invented to accomplish small input-referred offset voltage ( $\text{V}_{\mathrm{ off}}$ ) and improve PSRR of BGR. In the dynamic-biased EA, an intended negative-feedback loop does dominantly work on the reduction of $\text{V}_{\mathrm{ off}}$ and supply noise influx. Simulation results confirm that $\text{V}_{\mathrm{ off}}$ of the proposed EA represents 2.3% distribution whereas each $\text{V}_{\mathrm{ off}}$ of the separate biased EA and the conventional EA shows 4.8% and 15% distributions, respectively. And the PSRR of the proposed EA-based BGR is increased by 23 dB comparing with the separate biased EA-based BGR around 2.5 MHz, and by 34 dB comparing with the conventional biased EA-based BGR around 1 MHz. By adopting the proposed feedback-biased EA, the 40-nm CMOS BGR circuit has been implemented to achieve superior $3\sigma $ inaccuracy of 1.1% and temperature variation of 13 ppm/°C without trimming.

This paper focuses on observing the aging impact of a DC offset cancellation circuit (DCOC) on the performance of an amplifier subject to time-based degradation, also known as aging. The circuit can be activated or deactivated to reduce the offset voltage that arises due to possible mismatches between the aging transistor in an amplifier. The proposed DCOC is designed along with a fully differential amplifier. It is fabricated in the low power TSMC 40 nm CMOS technology by using a single power supply of 1.1 V. Post-layout simulation results demonstrate that the offset suppression can be realized both in the Monte Carlo (MC) and corner analysis. In the measurement results of the fabricated chips, the DC offset, which is present before the deactivation of the DCOC, is suppressed by 19.25 dB.

A Space Vector Pulse Width Modulation (SVPWM) control strategy is proposed for a three phase five level dual inverter fed open-end winding induction motor. This system includes 2 three level Neutral Point Clamped (NPC) inverters, which is supplied by two isolated dc power supplies. The conventional SVPWM has more complexity in reference vector identification and switching time calculation. The reference vector for proposed five level SVPWM scheme is tracked using three level voltage vector and offset voltage, where 5-level hexagonal region is divided into seven 3-level hexagonal regions. The proposed SVPWM leads to reduce the complexity in switching time calculation, Total Harmonic Distortion (THD) reduction, Minimization of Common Mode Voltage (CMV) and low voltage stresses across the switching devices. Also this system estimate the phase current of the five level dual inverter fed open-end winding induction motor. The results obtained using simulation and hardware are compared and verified using Digital Signal Processor.

The charge amplifier is an important building block in various electronic circuits. In this paper a new charge amplifier for piezoelectric sensors is introduced. The advantages of the new proposed charge amplifier becomes obvious in the quasi-static applications. In some quasi-static applications the traditional charge amplifiers uses an extremely large feedback resistor (in the range of $\text{G}\Omega $ ) whereas the proposed charge amplifier no longer requires such extremely large resistors. Moreover the proposed circuit reduces the output offset voltage significantly in comparison with conventional charge amplifier. The proposed circuit can be also implemented by using general purpose JFET operational amplifiers instead of using electrometer operational amplifiers therefore the cost of implementation will be reduced significantly in comparison with conventional charge amplifier. The proposed charge amplifier was assembled by using general purpose JFET Op-Amp to capture and amplify the output voltage of the piezoelectric vibration sensor Minisense100. In this experiment the low-cutoff frequency and the gain of the proposed charge amplifier were set equal to 0.2Hz and 20.5 dB respectively. The output offset voltage of the circuit was measured equal to 210 $\mu \text{V}$ .The measurement of very small vibration (±0.015g) showed a relative error equal to 2.1% with respect to the value which is obtained by using vibration meter as reference.

In this paper, an improved self-biased bandgap reference (BGR) with high power supply rejection ratio (PSRR) is presented. An operational amplifier constructing feedback loop is multiplexed with the generation of positive temperature coefficient (TC) voltage for lower power consumption, where an offset voltage is adopted to achieve proportional to absolute temperature (PTAT) voltage. With the temperature-independent reference generation, two feedback loops are realized at the same time for PSRR enhancement, which form a local negative feedback loop (LNFL) and a global self-biased loop (GSBL). The proposed BGR is implemented in a 180 nm BCD technology, whose results show that the generated reference voltage is 2.506 V, and the TC is 25 ppm/°C in the temperature range of −55 to 125 °C. The line sensitivity (LS) is 0.08 ‰/V. Without any filter capacitor, the PSRR is 76 dB at low frequencies, over 46 dB up to 1 MHz.

Biopotential amplifier (BPA) remains one of the most crucial blocks for the successful implementation of any of the biomedical systems. However, design of a BPA remains challenging owing to most of the topologies reported in literature displaying high values of noise, consuming high value of power and working in limited range of bandwidth. Thus, circuit topologies capable of providing an optimum and an acceptable combination of these parameters remains a topic of immense interest among researchers. We in this paper, report the results of a BPA designed using Bulk-Driven Quasi-Floating Gate (BDQFG) technique with a special focus on the effect of variation in the values of biasing resistor (Rlarge). Results obtained through mathematical modelling and analysis of the circuit have been verified by conducting simulations in Cadence Analog Design Environment using standard 0.18 µm technology. Circuit design has been optimized for least values of power consumption of the order of 1.1 µW, noise (≈ 3.15 µVRMS), mid-band gain of 39.9 dB (from 0.266 Hz to f-3dB of 2.8 kHz), offset voltage of 455 μV and phase margin of 65.83°.

Nowadays, high-frequency switching power amplifiers (SPA) have been studied widely; bulk of the researches were focused on audio power amplifiers. In active magnetic bearing (AMB) systems, high-frequency electromagnetic excitation caused by rotor imbalance can affect the performance of the SPA, so the traditional SPA cannot meet the requirements of the AMB systems. Therefore, on the premise of ensuring larger power, the frequency of the SPA should be improved to ensure the normal operation of the AMB system. Two-level pulsewidth modulation (PWM) current-mode SPAs are widely used in AMB systems. In order to broaden the bandwidth and to reduce the average steady-state error current, SiC power devices based SPA with a high bus voltage and a high switching frequency was designed. The basic principle and the linearized control model of SPAs are introduced. Then, the duty ratio stability and average steady-state error current of the SPAs are analyzed based on the output ripple current. When the PWM modulator is designed by either the discrete devices or the integrated chips, the critical gains to ensure the duty ratio stability are, respectively, analyzed based on the slope matching and the nonideal characteristic of operational amplifiers. Hence, two methods to reduce the average steady-state error current are proposed, respectively. One is to adjust the offset voltage of triangular carrier for the P controller, the other is to use a proportional integral (PI) controller. The offset adjusting method allows the SPA to achieve better dynamic performance and wider bandwidth. The proportional integral (PI) controller can reduce the average steady-state error current but narrows the bandwidth. Finally, the experiment results are in good agreement with the theoretical analyses.

The basic principles of reference voltage source construction are considered in the article. Possible sources of error of the output reference voltage, advantages and disadvantages of the existing architectural solutions of the reference voltage sources are analyzed. An architectural solution for the construction of a reference voltage source with higher order nonlinearities compensation is proposed, which has a temperature independent output voltage and is capable of operating at a supply voltage equal to or below 1 V. This solution has the possibility of implementing in the standard CMOS technology. Recommendations for compensation for the error caused by the offset voltage of the operational amplifier are given. In the modern world, integrated circuits (ICs) are the nucleus of virtually all electronic systems. When designing many ICs, one of the most important tasks is to generate accurate voltages for the entire circuit. The ICs that create these voltages are often referred to as the reference voltage sources. The reference voltage is a major component of both fully analog and digital circuits and even memory elements. There is a particular demand for low voltage power supplies as it is required for modern gadgets, mobile phones, laptops, cameras, etc. They should have low sensitivity to changes in power supply, possible deviations in the parameters of the manufacturing process and temperature. The reference voltage sources in standard CMOS technology have high precision output voltage, but temperature dependence is a problem. Another problem of such circuits is the inability to operate with a supply voltage below 1 V. The reasons for this are two: the principle of their operation is based on a bandgap of silicon equal to 1.25 V, which already exceeds 1 V of power; the second reason is that low voltage sources of reference voltage contain an operational amplifier, which should also operate at low power. In this case, low voltage power supply generators have poorer accuracy rates than classical implementation. Therefore, improving the characteristics of reference voltage sources while being able to operate at a supply voltage close to or below 1 V is a problem and requires a compromise solution. In the article was analyzed generators that provides proportional to absolute temperature (PTAT) voltage at their outputs, generators that provides complementary to absolute temperature (CTAT) voltage at their outputs. The source of the high-order nonlinearity was analyzed. The schematic of implementing reference voltage generators was proposed. The formulas for output voltage was derivated. The basic principles of operation of proposed schematic was described. The voltage reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction transistor devices in the CMOS process, is presented.

The simplest input is a switch, with an array of switches forming a numerical keypad input. Timers and interrupts are often used in input processing, such as debouncing. An LED is a simple output indicator, which can be used in a seven-segment display to provide a simple character display. The LCD provides a more versatile alphanumeric output.