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Opens are known to be one of the predominant defects in nanoscale technologies. With an increasing number of complex cells in today’s very large-scale integration designs intracell opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOFs) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. Furthermore, generated tests might be invalidated in case hazards and charge-sharing are not properly considered. In this paper, we present a waveform-accurate SAT-based automatic test pattern generation (ATPG) framework to tackle these problems. The proposed method not only allows for the generation of tests that are robust against hazards and charge-sharing, it can also be used to generate tests for faults only detectable by hazard-based activation—and hence even increase the fault coverage beyond state-of-the-art cell-aware tests. Our experimental results for the largest ITC’99, IWLS 2005 as well as larger industrial circuits mapped to the state-of-the-art NanGate 45-nm as well as NanGate 15-nm cell library using complex cells show the high efficiency and scalability of the proposed method. For example, the results show that without properly considering hazards and charge-sharing up to 17.9% of the generated tests could be invalidated. In addition, hazard-activated ATPG allows to detect an additional 10.1% of conventionally undetectable faults that could result in a very significant defective parts per million improvement.

In this study, we propose complementary metal-oxide−semiconductor (CMOS) NOR logic gates consisting of silicon nanowire (NW) arrays on bendable substrates. A circuit consisting of two p-channel NW field-effect transistors (NWFETs) in series and two n-channel NWFETs in parallel is constructed to operate a two-input CMOS NOR logic gate. The NOR logic gates operate at a low supply voltage of 1 V with a rail-to-rail logic swing and a high voltage gain of approximately −3.0. The exact NOR logic functionality is achieved owing to the superior electrical characteristics of the well-aligned p- and n-NWFETs, which are obtained using conventional Si-based CMOS technology. Moreover, the NOR logic gates exhibit stable characteristics and have good mechanical properties. The proposed bendable NW CMOS NOR logic gates are promising building blocks for future bendable integrated electronics.

The 3D stacked hybrid memory relies on a hysteretic Nano-Electro-Mechanical Field Effect Transistor (NEMFET) inverter to store data, and on adjacent CMOS based logic to allow for read/write operations, and data preservation. In this paper we assess the feasibility of a hybrid memory cell, and explore the design space of 3D stacked hybrid dual-port memory arrays which combine the appealing NEMFET properties, i.e., ultra-low leakage currents and abrupt switching, with the CMOS technology versatility. In the evaluation we performed a comparison in terms of footprint, access time, and energy, against state of the art CMOS dual-ports memories, considering small and large size memory arrays ( $8$ -Kbytes up to $128$ -Kbytes) implemented in various technology nodes. The 3D NEMFET-CMOS hybrid dual-port memory is on the average $25$ percent smaller and $8$ and $95$ percent larger in terms of footprint when compared to $90$ , and $45$ nm CMOS implementations, respectively. The write access time is approximately $2\times$ higher, as it is dominated by the mechanical movement of the NEMFET's suspended gate, while the read access time is about $12$ percent lower, when compared with $45$ nm CMOS counterparts. For small size memories our proposal results in at least $15$ percent and $23$ percent energy reductions for $100$ and $50$ percent data transition probability, respectively. For large size memories an energy reduction of about $40$ percent was obtained, as in this case the static energy is predominant.

Spintronics-based devices and circuits attract massive research interest from both academia and industry. A number of the devices and logic circuits have been proposed such as spin-based magnetic tunnel junction and all spin logic gate. A fundamental spin-based device, spin field-effect transistor (spin-FET) is one of the most interesting spin-based devices to address the power issue of semiconductor transistors which is still a research focus. In this paper, we first present an electrical model for the spin-FET based on both theoretical and experimental results. The theories of spin injection and detection are considered by a current driver of the spin-FET. Gate voltage modulation following Datta–Das theory is combined with the experimental results from several works of literature. Afterward, through the dc analysis of two spin-FETs with different channel materials, we demonstrate that the channel using InAs is a better choice to make a feasible spin-FET. The channel length is also optimized by the comparison of simulation results. Finally, a local geometry spin-FET model suitable for logic design is implemented with Verilog-A language and integrated on Cadence platform. Using our model, a low-power inverter is designed based on the concept of complementary spin-FET, and a logic circuit is proposed to implement AND and NOR logic functions. Simulation results validate the behaviors of the logic circuits and availability of our model.

Benefitting from its non-volatility, nearly infinite endurance, good scalability, and great CMOS compatibility, magnetic tunnel junction (MTJ) embedded in conventional CMOS logic circuits has been proposed as one potentially powerful solution to introduce non-volatility in today’s programmable logic circuits, which is envisioned to achieve low power and high area efficiency. However, the recently proposed hybrid CMOS/MTJ logic circuits and prototypes based on such a logic-in-memory architecture suffers from a severe reliability issue, which is the precise transformation from MTJ resistance to electric signals due to its limited tunnel magnetoresistance ratio (TMR $\leq$ 150%), i.e., the requirement of nearly zero sensing error for logic applications. In this paper, to overcome this sensing reliability issue, a novel sense amplifier (SA) with high sensing margin is proposed for such hybrid CMOS/MTJ logic circuit architecture. By using a commercial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ transient and Monte Carlo statistic simulations have been conducted to demonstrate the functionality of the proposed SA and evaluate its performance, respectively.

Benefitting from its non-volatility, low power, high speed, nearly infinite endurance, good scalability, and great CMOS compatibility, magnetic tunnel junction (MTJ) embedded in conventional CMOS logic circuits has been proposed as one potentially powerful solution to introduce non-volatility in today’s programmable logic circuits, which is envisioned to extend Moore’s law. However, a critical issue in such hybrid CMOS/MTJ logic circuit is the reliable transmission of MTJ electric signals to the CMOS electronics, i.e., the requirement of nearly zero read/write error for logic applications. In this paper, a reliability-enhanced separated pre-charge sensing amplifier (RESPCSA) is proposed for hybrid CMOS/MTJ logic circuits. By adding two feedback paths with only two transistors between its discharge and evaluation terminal, such proposed RESPCSA can achieve a more and more larger dynamic resistance difference between its two discharge branches with the MTJs during the discharge phase, thereby obtaining a large sensing margin. By using a commercial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ transient and Monte-Carlo statistic simulations have been conducted to demonstrate its functionality and evaluate its performance, respectively.

In this paper, implication (IMP) operations are demonstrated in a circuit with two SiOx-based memristors and a CMOS transistor. Specifically, a circuit with two one-diode and one-resistor (1D1R) memory elements and a transistor are designed to perform the IMP operations. A circuit consisting of a $4 \times 4$ crossbar 1D1R memristor array together with selection transistors is proposed and used to realize the functionality of a one-bit, full adder in 43 steps. Compared with CMOS logic circuits, the advantages and disadvantages of memristor-enabled logic circuits are discussed. This result suggests that the memristor-enabled logic circuit is most suitable for low-power and high-density applications, as well as a simple and robust approach to realize programmable memcomputing chips compatible with large-scale CMOS manufacturing technology.

As a first step to develop a diamond integrated circuit, hydrogenated diamond not and nor logic circuits composed of depletion-mode (D-mode) and enhancement-mode (E-mode) metal–oxide–semiconductor field-effect transistors (MOSFETs) are fabricated. The D- and E-modes MOSFETs act as load and driver devices for the logic circuits, respectively, which provides complementary transistor actions. The extrinsic transconductance maxima for both the MOSFETs are almost the same value of 17 mS mm $^{-1}$ and insensitive to device processing. With supply voltage changing from −5 to −25 V, gain maximum for not logic circuit increases from 1.2 to 26.1. The nor logic circuit shows clear nor gate characteristics.

Parallel and monolithic three-dimensional (3-D) integration directions realize 3-D integrated circuits (ICs) by utilizing layer-by-layer implementations, with each functional layer being composed in 2-D. In contrast, vertically composed 3-D CMOS has eluded us likely due to the seemingly insurmountable requirement of highly customized complex routing and regional 3-D doping to form and connect CMOS pull-up and pull-down networks in 3-D. In the current layer-by-layer directions, routing can be worse than 2D CMOS because of the limited pin access. In this paper, we propose Skybridge-3D-CMOS (S3DC), an IC fabric that shows for the first time a pathway to achieve fine-grained static CMOS circuit implementations using the vertical direction while also solving 3-D routability. It employs a new fabric assembly scheme based on predoped vertical nanowire bundles. It implements circuits in and across nanowires. It utilizes unique connectivity features to achieve CMOS connectivity in 3-D with excellent routability. As compared to the usually severely congested monolithic 3-D implementations, S3DC eliminates the routing congestions in all benchmarks studied. Further results, for the implemented benchmarks, show 56–77% reductions in power consumption, 4X–90X increases in density, and 20% loss to 9% benefit in best operating frequencies compared with the transistor-level monolithic 3-D technology.

In this paper, a floating-gate tribotronic transistor (FGTT) based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor (FET) is proposed. In the FGTT, the triboelectric charges in the layer created by contact electrification can be used to modulate charge carrier transport in the transistor. Based on the FGTTs and FETs, a tribotronic negated AND (NAND) gate that achieves mechanical-electrical coupled inputs, logic operations, and electrical level outputs is fabricated. By further integrating tribotronic NAND gates with traditional digital circuits, several basic units such as the tribotronic S-R trigger, D trigger, and T trigger have been demonstrated. Additionally, tribotronic sequential logic circuits such as registers and counters have also been integrated to enable external contact triggered storage and computation. In contrast to the conventional sequential logic units controlled by electrical signals, contact-triggered tribotronic sequential logic circuits are able to realize direct interaction and integration with the external environment. This development can lead to their potential application in micro/nano-sensors, electromechanical storage, interactive control, and intelligent instrumentation.

Flexibleelectronics based on thin-film transistors (TFTs) are promising in the area of Internet of Things and wearable devices, where the pseudo-CMOS logic is widely used in the unipolar TFT circuits. Though plenty of device models exist, analytical circuit-level models are still absent, preventing the further development of design and analysis of flexible TFT circuits. In this paper, we derive the noise margin (NM), delay, and power models for pseudo-CMOS logic circuits. Furthermore, we simplify thosemodels formanual analysis and design optimization. Allmodels are validated by SPICE simulations, where the device model and its parameters are extracted from the fabricated self-assembled monolayer organic TFTs. The average errors for NM, delay, and power models are 3%, 10%, and 3%, respectively. In addition, we exploit the delay models in a voltage-controlled oscillator design and its linearity of frequency characteristic is optimized with the proposed models, demonstrating their effectiveness.

A new unipolar differential logic (UDL) for the large-scale integration of amorphous In-Ga-Zn-O (aIGZO) digital circuits is proposed. Only single-threshold single-gate and aIGZO thin-film transistors are required. The proposed UDL logic gates are very insensitive to transistor parameter variations (i.e., threshold voltage, mobility, off-current, and subthreshold slope), which are inherently due to large-area low-temperature fabrication processes and operating conditions. To assess the UDL effectiveness, a wide range of parameter variations is considered: and, owing to the proposed architecture up to 1.5 $\times$ 107 UDL gates that can be integrated with a yield that is greater than 90%.

This brief introduces a mixed-logic design method for line decoders, combining transmission gate logic, pass transistor dual-value logic, and static complementary metal-oxide semiconductor (CMOS). Two novel topologies are presented for the 2-4 decoder: a 14-transistor topology aiming on minimizing transistor count and power dissipation and a 15-transistor topology aiming on high power-delay performance. Both normal and inverting decoders are implemented in each case, yielding a total of four new designs. Furthermore, four new 4-16 decoders are designed by using mixed-logic 2-4 predecoders combined with standard CMOS postdecoder. All proposed decoders have full-swinging capability and reduced transistor count compared to their conventional CMOS counterparts. Finally, a variety of comparative spice simulations at 32 nm shows that the proposed circuits present a significant improvement in power and delay, outperforming CMOS in almost all cases.

Memristor-based material implication (M-IMP) logic is popular with logic operations, which provides a possibility that memory is operated directly. However, there is a small limitation that memristor is not able to reach the lowest resistance in M-IMP. In this brief, the M-IMP limitation and its influence are analyzed briefly. In addition, a circuit structure that performs a stateful logic operation on memristor memory based on a nanocrossbar is proposed, which can perfect the M-IMP limitation and eliminate the influence. Moreover, we simulate the proposed circuit design and the simulation results verify the correctness of the analysis.

In the history of electronics, solid-state materials replaced the vacuum parts to reduce power consumption and to obtain better reliability at a reduced cost. The size of solid-state transistors continued to reduce since its introduction, and currently, we have transistors with dimensions on the order of $\sim$ 10 nm. This downscaling of transistor dimension accompanied with proportionate changes in supply voltage so that the overall power consumption stays below a tolerable limit. The situation dramatically changed when requirements of proper electrostatic control over the entire length of the transistor and its reliable operation stopped supply voltage scaling, increased off -state leakage, and hence caused exponential increase in power consumption. The introduction of a high- $\kappa$ gate dielectric and then a multiple/surround gate within the CMOS architecture have improved the situation, but still have not provided the complete solution for the future. For future electronic devices, we need switches with extremely low off -state leakage, small supply voltage, and high-drive current without compromising the yield and reliability currently available in modern-day nanoscale transistors. The available options are based on extensions of current CMOS transistors by using nanowires, III–V compounds, carbon nanomaterials, transition metal dichalcogenides as channel, ferroelectrics as dielectric, and ferromagnets as source/drain. On the other hand, device architectures that are completely different from conventional CMOS (so-called beyond CMOS devices) such as tunnel transistors, nanoelectromechanical devices, and impact ionization transistors are also under consideration for future electronics. The performance of many of these beyond CMOS devices is yet to be comparable to that obtained in the current-day CMOS transistors. In addition, many of these proposed devices have a number of classical and some novel reliability concerns. This review article presents reliability concerns for a set of extended and beyond CMOS devices and shows that defects in different parts of these devices require detailed study to ensure their usability in electronics industry. Therefore, in addition to the current ongoing research to obtain better performance using the proposed devices, a parallel reliability analysis is also needed. This kind of early-stage reliability analysis may reveal whether any reliability concern is intrinsically related to the device design—hence suggests us to look for alternative device concepts for future CMOS.

The high power and the long global interconnect delay are two of the major bottlenecks that limit the further scaling down of the process nodes in the VLSI systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and the interconnect delay. Current-induced magnetic domain-wall (DW) racetrack memory (RM) has the advantages of nonvolatility, fast switching speed, and high density. It may offer opportunities to open a new paradigm of circuits and architectures to significantly alleviate the power and delay issues. This paper presents the magnetic DW RM-based new nonvolatile logic designs for the low-power computing and fast run-time-reconfiguration. Both data transfer and reconfiguration are achieved by shifting the magnetic strips. Verify-before-shift approach is used to greatly reduce the shifting energy. Compared with the conventional nonvolatile logic gate, the proposed nonvolatile logic scheme doubles the operating speed with 87% lower operating energy. Moreover, the proposed nonvolatile logic gates can be reconfigured after fabrication, which makes the designs more flexible and robust. The reference reconfiguration and the polarity reconfiguration are presented in this paper, which can be finished in 1 ns with 130 fJ/strip energy and 6 ns with 390 fJ/strip energy, respectively.

In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, single-output, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The library consists of a small number of cells, each of which can compute a set of complex threshold functions, which would otherwise require a multilevel network. The function realized by a given threshold gate is determined by how signals are mapped to its inputs. We present a method for the assignment of signals to the inputs of a threshold gate to realize a given threshold function. Next, we present an algorithm that replaces a subset of flip-flops and portions of their logic cones in a conventional logic netlist, with threshold gates from the library. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. We demonstrate significant reductions (using postlayout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.

Photonic integrated circuits (PICs) will be pushed to electronic integrated circuits in the forthcoming decade because of its package density, interconnections, improved functionality and cost effectiveness. In this study, the authors propose a new configuration of photonic crystal (PhC) integrated circuits to realise the operation of all-optical logic AND function that operates at a speed of hundreds of gigabits per second. The integrated circuit comprises of lasers, waveguide couplers, logic gate, amplifier and threshold limiter in a two-dimensional (2D) silicon PhC platform. The behaviour of the proposed structure is qualitatively analysed by the use of 2D finite-difference time-domain method. The results show that the integrated circuit performs the required logic operation. The average area required for the entire device including regenerated circuit is 25 × 10 μm 2 . The overall response time is

In the last decades, the CMOS technology has undergone an extraordinary evolution. Because of the continuous scaling process, CMOS transistors are now so small that millions can be easily fitted in a single chip. Shrinking transistor sizes have complex consequences on the performance of both the transistor itself and the system that is based upon it. Understanding and teaching the CMOS scaling process and its consequences on circuits are an increasingly difficult task. Furthermore, the scaling process is reaching an end, due to the continuously growing fabrication costs and the unavoidable physical limits on the smallest size achievable. As a consequence, many emerging technologies, such as carbon nanotubes and nanowires, are being studied as possible CMOS substitutes. Describing and teaching these new technologies, alongside the scaled transistor itself, adopting a complete and well-organized approach is a process that presents further difficulties. To solve these problems, we have started in the past years the development of TAMTAMS, a tool conceived to analyze CMOS circuits, from device to system level. The tool is based on models derived from the literature or, in some cases, internally developed and verified. It allows to analyze the main characteristics of a CMOS transistor, such as currents, threshold voltage, or mobility, considering different technology nodes and parameters, and to understand how they influence the circuits performance. The tool structure is open and modular, allowing, therefore, easy integration of further CMOS technologies and to compare them. In this paper, we present a total overview of the original tool, TAMTAMS Web. While the general concept behind the tool is still the same, the tool was completely rewritten around a Web interface. TAMTAMS Web is freely accessible to students and to any one interested in CMOS technology. As a future development, several post-CMOS technologies will be added to TAMTAMs Web, allowing, therefore, a comparison with the state-of-the-art CMOS. TAMTAMS Web is actively used in the Integrated System Technology (IST) held at the Politecnico di Torino. It defines a new way of learning, because students learn and understand the modern electronic technology both using TAMTAMS Web as an instrument, and being part of the development process, as part of the IST course.

This paper proposes accurate CMOS device de-embedding and modeling methods. For millimeter-wave circuit design, accurate simulation models are required. For this reason, an accurate measurement is a key technique for device characterization, and de-embedding and modeling methods are also very important. In this work, a three-parameter pad model based on L-2L de-embedding method and a transistor model with frequency and bias dependency are proposed. The pad model is derived from the assumption that the capacitance of PADs becomes constant at high frequencies. In the transistor modeling, parasitic elements are extracted mathematically. A five-stage low-noise amplifier is fabricated by 65–nm CMOS technology to confirm the accuracy of simulation, and the simulation and measurement results match well with each other.

In present day skill, designing of low power systems has emerged as one of the vital theme of electronic industries due to the point that, power consumption is drawing much of the absorption in any very large scale integration (VLSI) chip design. Design of low power circuit for high performance is the necessary main concern of VLSI technique. This paper presents designing of Half Subtractor using basic gates which are drawn by conventional CMOS and Pass Transistor Logics based on 45nm technology . In comparison between the conventional CMOS half subtractor and using Pass Transistor Logic the delay is 10.5% less in PTL"s half subtractor which is due to less number of transistors used in Pass Transistor Logic which in further has reduced the transistor count to 28.57%. Keywordssubtractor, pass transistor logic, digital circuits.

Static virtual ground voltage $(V_\mathrm{gnd})$ is an important parameter to be accurately and efficiently estimated for fine-grained power gating in logic circuits. Previous work results in a large error in $V_\mathrm{gnd}$ estimation due to conservative leakage models and inaccurate assumption of voltage conditions at the input of CMOS gates in power-gated circuits. To overcome these problems, we propose support vector machine (SVM)-based macromodels to estimate the leakage current of CMOS gates and thus achieve effective reduction in error in leakage model characterization. These models are then used in SVM classifier (SVC) and regressor to formulate an SVM regression-based $V_\mathrm{gnd}$ model. The SVC results in 3 $\times$ savings in data generation time compared with HSPICE simulation to develop the final $V_\mathrm{gnd}$ model. The proposed model results in < 1% error and 23 000 times the speedup than HSPICE for the largest benchmark circuit.

Silicon Carbide (SiC) is an attractive candidate for integrated circuits (ICs) in harsh environment applications due to its superior inherent electrical properties. Though current research is geared towards adapting existing silicon based digital logic technologies to 4H-SiC, the true merit of each technology in 4H-SiC has remained unclear. Creating logic technologies specifically for 4H-SiC, taking into account its electrical properties, is an area which remains unexplored. In this paper, we present a novel bipolar logic technology that is designed and optimized for 4H-SiC, and compare its performance with the prevalent bipolar technologies. The results show that the novel logic technology not only compares well with the conventional technologies in performance, but also features simpler design, smaller footprint, and a low transistor count.

Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style is robust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is often found in critical paths of various large scale high performance circuits. Yet, due to high switching activity they are not suitable for synthesis of low power circuits. To achieve both power and speed benefits, we propose a method of designing circuit using mixed CMOS logic style, taking advantages of both static and Domino logic styles. For a given circuit, we extract the unate and binate components using a unate decomposition algorithm. These are optimized such that the resulting circuit is optimum in terms of power, area and delay. To do this, a multi-objective genetic algorithm is employed. The optimized unate and binate blocks are mapped using Domino and static cell libraries, respectively. Testing the efficacy of our approach with ISCAS85 and MCNC89 benchmark circuits showed an improvement of 25% in delay and 22% in transistor count with 12% more power dissipation compared to circuits with only static CMOS logic. Thus, mixed CMOS circuits are promising in high speed and area constraint applications.

High performance and stable operation are desired features of today’s integrated circuits (ICs). Due to its inherent properties, devices based on silicon carbide (SiC) exhibit excellent temperature and radiation tolerance, with performance levels similar to or better than the ones in silicon (Si). Instead of specifically creating circuit topologies suited for SiC, current research efforts are focused on adapting existing Si-based technologies to SiC. In this letter, we report a novel bipolar logic technology designed to exploit the electrical characteristics of 4H-SiC and to outperform conventional technologies. It has fewer transistors, simpler topology, and features simple-to-design complex gates. The circuit shows simulated gate delays as low as 3.3 ns at 27 °C/4.2 ns at 500 °C and noise margins higher than 1 V at 27 °C–500 °C. The proposed technology performs remarkably well across all performance parameters, validating its potential for cost effective, smaller footprint, simple to design, and easily reconfigurable digital ICs in SiC for small-scale logic applications.

The subthreshold region of operation in digital CMOS circuits provides a suitable low-power solution for many applications that need tremendously low-energy operation. However, this advantage comes at the cost of speed, so enhancing the speed of subthreshold circuits can expand their application spectrum. This paper presents the optimum pMOS-to-nMOS width ratio that leads to the maximum frequency of operation in the subthreshold region with no extra energy cost. The optimum pMOS-to-nMOS width ratio is obtained and compared through three approaches: 1) finding the maximum current-over-capacitance ratio of a biased transistor; 2) deriving an analytical expression by minimizing the delay of an inverter; and 3) simulating different CMOS logic gates in the subthreshold region. Simulation results illustrate that in the subthreshold region, the frequency attains its maximum at the optimum pMOS-to-nMOS width ratio independent of the supply voltage. Using this optimum value in designing a carry-look-ahead adder improves the propagation delay, energy consumption, and energy-delay product by up to 33%, 36%, and 57%, receptively, compared with when the conventional pMOS-to-nMOS width ratio (in the superthreshold region) is used. We verified our analytical model by performing circuit simulations in four CMOS technologies (TSMC 180 nm, IBM 130 nm, TSMC 90 nm, and ST 65 nm).

This paper introduces two new cells for logic-in-memory (LiM) operation. The first novelty of these cells is the resistive random access memory configuration that utilizes a programmable metallization cell as nonvolatile element. CMOS transistors and ambipolar transistors are used as processing and control elements for the logic operations of the LiM cells. The first cell employs ambipolar transistors and CMOS in its logic circuit (7T2A1P), while the second LiM cell uses only MOSFETs (9T1P) to implement logic functions, such as AND, OR, and XOR. The operational mode of the proposed cells is voltage-based, which is much different from the previous designs in which a LiM cell operates on a current mode. Extensive simulation results using HSPICE are provided for the evaluation of these cells; comparison shows that the proposed two cells outperform previous LiM cells in metrics, such as logic operation delays, power delay product, circuit complexity, write time, and output swing.

Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series–parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.