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NbN RSFQ circuits operating at 9 K reduce the cooling constraints especially for portable, remote, telecoms or medical imaging applications. We have developed a test-bed to study the operating temperature of the various mixed RF and digital circuit blocks of NbN `HyperSCAN' project test vehicle 1 cm2 chips. The use of a widespread helium cryostat (`Orange-ILL') allows us to stabilize the chip temperature in the range 2.9 K-20 K with thermal oscillations lower than 0.1 K. The chip is mounted on a PCB and shielded from the external field: the PCB provides a multi-connection packaging used in order to study temperature and frequency operation of 30 GHz NbTiN CPW filters, RSFQ gates, analog SQUID and NbN/TaN/NbN SNS junctions arrays. The comparison between electrical simulations and tests is made on flexible, ~ 56 cm long, micro-strip line ribbon cable carrying 32 signals each including bias lines, in the range of DC-3 GHz, combined with 4 semi-rigid ~ 40 GHz coaxial cables. By removing spurious resonances, it is expected to take full benefit of the large bandwidth, low insertion loss and low thermal conductivity of the set-up. We emphasis on the flexibility, large yield, reliability and reduced cost of such packaging coupled to He cooling exchanger for applying to testers and to future 9 K NbN multi-ADC green and remote systems when only low electrical power sources are available.

NbN-TaN-Nb(Ti)N non-hysteretic SNS Josephson junctions with TaXN barriers tuned through nitrogen content at metal-insulator transition have been produced in a reliable way with characteristic voltage RNIC above 1.5 mV at 9 K. Barriers are typically 7-10 nm thick and Jc in the range 5 to 25 kA/cm-2 making feasible LSI RSFQ ADC circuit integration by using the lithographic tools of the Leti C-MOS platform. Junction tri-layers, NbTiN ground-plane and wiring levels have been reactively sputtered and optimized at 300°C in a reproducible way on 8-inch oxidized silicon wafers. A deep UV stepper combined with SF6 gas mixtures RIE has been used to achieve low spread lithography in junction diameters of 716 nm (3σ ~ 40 nm), of 465 nm (3σ ~ 84 nm) across the 8-inch. A well controlled CMP planarization process has been developed on thick PE-CVD silica layers deposited on each superconducting nitride layer. On-line FIB-SEM observations and electrical characterizations associated to the development of a technology test vehicle demonstrate the feasibility of the complete process. The reliable production of nitrides LSI RSFQ circuits such as ADCs and integrated imagers operating in a relaxed cryogenic environment in the 6-10 K temperature range is foreseen to open new telecoms and medical applications. Moreover, a new MgO-AlN-MgO layered insulating barrier junction is shown to operate above 10 K and will be developed for analog front-end circuit parts.

Process test chips for Josephson integrated Circuits including refractory metal resistors have been achieved and tested with Niobium based technology made in LETI. Tantalum resistors are lying above niobium base electrode. Such a configuration gives compact logic circuits and very good mechanical bahaviours. An entire 14 layers technology including Nb-Nb 2 O 5 - Pb(In) tunnel junctions, control lines and contact pads is being achieved and described. Arrays of 100 interferometers cells, superconductive contacts in series, and other chips for measuring capacitance of junctions and insulators, penetration depths in superconductive materials, resistors are fabricated on sapphire, wafers and tested. Such devices yield a good stability upon thermal cycling and storage at room temperature.

All-Niobium Nitride Josephson junctions have been prepared successfully using a new processing called SNOP : Selective Niobium (Nitride) Overlap Process. Such a process involves the "trilayer" deposition on the whole wafer before selective patterning of the electrodes by optically controlled Dry Reactive Ion Etching. Only two photomask levels are need to define an "overlap" or a "cross-type" junction with a good accuracy. The properties of the Niobium Nitride films deposited by DC-Magnetron sputtering and the surface oxide growth are analysed. The most critical point to obtain high quality and high gap value junctions resides in the early stage of the NbN counterelectrode growth. Some possibilities to overcome such a handicap exist even if the fabrication needs substrate temperatures below 250 °C.

High rate Dc-magnetron sputtering of 30 nm niobium thin films is shown to be a very good technique to achieve reproducible and stable ground plane, tunnel junctions electrodes, control lines and even resistors for Josepson Integrated Circuits. Pure niobium films have low residual resistivity (ρ 10 k \simeq 2\mu \Omega cm), low stresses, and are no longer in the "dirty limit". High quality ratio ( R_{J}/R_{N} \simeq 20 at 4 K). Josephson Junctions were performed with niobium base electrode. Critical temperatures either below 4.2K used for resistors or between 4.2K and 16K can be controlled accurately by reactive magnetron sputtering in an argon-nitrogen plasma. Homogeneous low critical temperature can be also selectively obtained by liquid cathodization or by RF plasma post-treatments on a pure niobium film through a photoresist mask. Nb, Nb(N), Nb(O) and Nb (H) films are studied by TEM and X ray diffraction. The critical temperature change obtained can be explained by lattice BCC structure dilatation or distorsion and by impurities inclusion.

Planar dc SQUIDs have been made and tested. They consist of a 5mm × 5mm square with a 30μm to 100μm hole, the junctions being near the center of the device. The loop inductance is in the range of 100- 200 pH. The technology uses Nb/NbOx/Pb overlapped junctions and Ta shunt resistors. Coupling is discussed ; we show that the input coupling constant k cannot be obtained by direct measurements and an efficiency constant r = I 1 /nI i , is introduced where n is the number of turns of the input coil, I i the input current and I 1 the induced current in the SQUID loop. An experimental efficiency of about 50% has been obtained.

A detailed investigation of tunneling has been carried out on Nb-Nb 2 O 5 -Pb(In) junctions where the tunnel barrier is made-of Nb 2 O 5 thermal oxide with accurately controlled oxidation parameters. The oxide barrier appears as a n-type semiconductor with two Schottky barriers at the interfaces. The transport of charged oxygen vacancies is supposed to play a fundamental role in the oxidation process. The barrier potential φ and the tunnel resistance R have been related to the oxidation parameters. The junctions realized have sizes ranging from 4 to 104μm2, the Josephson current density, dependent on the oxide thickness, is in the 1-105A/cm2range. Very low transition times from the superconductive to the normal state have been observed.

This paper describes the fabrication and testing of a two-junction Josephson device which can be used as a DRO memory cell for the investigation of the feasability of a random access memory. The cell was fabricated by means of a 10-layers thin film process with Nb-Nb 2 O 5 -Pb(In) tunnel junctions. Quasi-static and dynamic experiments have been performed on these devices and compared to computer simulations. The agreement seems to be fairly good. Memory capability has been proven by successive write and destructive read out cycles in the quasi-static mode (up to 10 MHz). Very high speed transitions from superconductive to normal state initiated by current pulses in the control line have been observed to the limit (25 ps) of the test apparatus.