756 results on '"J. Murakami"'
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2. Exploring a Topical Representation of Documents for Recommendation Systems.
3. Preparation of Trifluoroacetate Metal Organic Deposition Derived REBa2Cu3O y Thin Film With High-J c and Low-R s for High-Power High-Temperature Superconducting Transmit Filters
4. On Clustering Algorithms: Applications in Word-Embedding Documents.
5. Semantic image retrieval for complex queries using a knowledge parser.
6. An intelligent annotation-based image retrieval system based on RDF descriptions.
7. Analyzing Brain Waves for Activity Recognition of Learners.
8. MAD7F: A FPGA-based CMP Memory Architecture Simulation Framework.
9. Guide Automatic Vectorization by means of Machine Learning: A Case Study of Tensor Contraction Kernels.
10. Towards activity recognition of learners by simple electroencephalographs.
11. A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias.
12. An Evaluation of a Complex Event Processing Engine.
13. Towards Activity Recognition of Learners by Kinect.
14. Towards Activity Recognition of Learners in On-line Lecture.
15. A survey on big data processing infrastructure: evolving role of FPGA.
16. Early stage power management for 3D FPGAs considering hierarchical routing resources.
17. A Smart Cyber-physical Systems-Based Solution for Pest Control (Work in Progress).
18. Using Machine Learning in Order to Improve Automatic SIMD Instruction Generation.
19. A Comparison of DAG and Mesh Topologies for Coarse-Grain Reconfigurable Array.
20. Methodology for early estimation of hierarchical routing resources in 3D FPGAs.
21. A Three-Dimensional Integrated Accelerator.
22. Routing architecture and algorithms for a superconductivity circuits-based computing hardware.
23. Performance evaluation of 3D stacked multi-core processors with temperature consideration.
24. A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack.
25. Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits.
26. Evaluation and optimization of Java object ordering schemes.
27. Correction to: Integrative Social Work Practice with Refugees, Asylum Seekers, and Other Forcibly Displaced Persons
28. A Call for a New Paradigm: Perspectives of Court Personnel and Clinicians on Court-Mandated Treatment Approaches for Domestic Violence Crimes
29. The Social Work Practitioner: Considerations for Working with Survivors of Forced Displacement
30. Culture, Trauma, and Loss: Integrative Social Work Practice with Refugees and Asylum Seekers
31. Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits.
32. Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units.
33. Empirical Performance Models for Java Workloads.
34. Performance balancing: software-based on-chip memory management for effective CMP executions.
35. A Dynamic Solution for Efficient MPI Collective Communications.
36. A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor.
37. Predicting Vectorization Profitability Using Binary Classification.
38. A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits.
39. Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension.
40. Design space exploration for a coarse grain accelerator.
41. Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection.
42. Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms.
43. The effect of temperature on cache size tuning for low energy embedded systems.
44. The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems.
45. Task scheduling for reliable cache architectures of multiprocessor systems.
46. Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.
47. Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator.
48. GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs.
49. Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit.
50. REDEFIS: a system with a redefinable instruction set processor.
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