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Techniques are presented for calculating the drain current of small-geometry MOSFET's in the linear, subthreshold, and punch-through regions of device operation. The current calculation depends only on the electrostatic solution of the two-dimensional Poisson equation in the device. The accuracy of the techniques is established by comparisons with full two-dimensional simulations based on the simultaneous solution of the Poisson and minority-carrier current-continuity equations. The results of simulation also agree well with measurements on MOSFET's having submicrometer effective channel lengths. The application of the simulations to nonplanar technologies is illustrated by the analysis of a taper-isolated dynamic-gain RAM cell. A description is given of simple numerical techniques for solving Poisson's equation in the presence of nonplanar boundaries. The solution method demonstrates good convergence characteristics and minimizes computer storage requirements. Consequently, the simulation capabilities have been successfully implemented on a desktop calculator (Hewlett-Packard 9845) and on minicomputers (Hewlett-Packard 2100 and 1000-F).

Results of experimental measurements and 2D computer modeling for submicron MOSFET's are presented. Statistical measurements are shown for MOSFET's with masked channel lengths ranging from 10.2 to 1.3 microns. It is shown by means of two-dimensional device analysis that the observed statistics are a result of both the design parameters such as junction profiles and variations in L eff due to process control.