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A factored form of a Boolean function is a common representation to express the complexity of a Boolean function in multi-level logic. However, a factored form which inhibits the appearance of the inversion operation is still a restricted way of representing a multi-level circuit. In this paper, we present a novel representation of a Boolean function, called the invert factored form representation. This representation mainly takes advantage of the inversion of whole or part of a Boolean function so that fewer literals and better multi-level circuit implementation can be obtained. Based on this novel presentation, our algorithm attempts to find a minimal expression. Experimental results also show the literal counts based on the novel representation are smaller than those on the traditional factored form representation.

A new test architecture, called TLS (tree-LFSR/SR), generates pseudo-exhaustive test patterns for both combinational and sequential VLSI circuit is presented. Instead of using a single scan chain, the proposed test architecture routes a scan tree driven by the LFSR to generate all possible input patterns for each output cone. The new test architecture is able to take advantages of both signal sharing and signal reuse. The benefits are: the difficulty of test architecture synthesis can be eased by accelerating the searching process of appropriate residues; and the number of XOR gates to satisfy the pseudo-exhaustive test criterion can be reduced. The TLS test scheme mainly contains three phases: backbone generation, tree growing, and XOR-tree generation. Experimental results obtained by simulating combinational and sequential benchmark circuits are very encouraging.