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1349 eginning with Stolzenberg [1] in 1980 and later popularized by Weiss et al. [2] in 1987, the apparent dilatation of the left ventricular cavity on myocardial perfusion imaging in the presence of extensive epicardial vessel stenoses has been referred to as transient ischemic dilation. Iskandrian et al. [3] provided evidence that the mechanism of this apparent dilatation may involve subendocardial ischemia by revealing increased wall thickness on the delay images when cavity dilatation with myocardial thinning was seen during stress. The severely ischemic, count-poor subendocardium at stress appears as part of the left ventricular cavity with an external rim of slightly better perfused epicardium. The result is a relatively dilated left ventricular cavity during stress imaging. Transient ischemic left ventricular cavity dilatation during stress myocardial perfusion imaging has become a generally accepted marker of severe, Causes of Transient Dilatation of the Left Ventricle During Myocardial Perfusion Imaging Vincent J. B. Robinson 1,2 , James H. Corley 2 , David S. Marks 1,3 , Linton W. Eberhardt 2 , Casimir Eubig 2 , George J. Burke 2 , L. Michael Prisant 1

The authors describe a general-purpose test and maintenance architecture for electronic subsystems and its demonstration in several avionics SEM-E modules for fiber-optic networking of the Advanced Tactical Fighter, A-12, and other modern aircraft. The results of applying this test and maintenance architecture are delineated in terms of payoff, penalty, and problems encountered. Industry efforts needed to eliminate some of the problems encountered are discussed. >

The Rapid Prototyping of Application Specific Signal Processors (RASSP) US Department of Defense (ARPA/Tri-Services) initiative is intended to dramatically improve the way digital systems, particularly embedded digital signal processors, are designed, manufactured, upgraded, and supported. These DSP systems are complex, with typically one or more printed circuit boards, a variety of implementation technologies and interfaces, and a wide range of data rates. The target RASSP improvement is at least a fourfold (4/spl times/) reduction in the time to go from design concept to fielded system. Equivalent improvements in cost and quality are also targets. The motivation for the RASSP initiative is the pervasive need for affordable embedded signal processors throughout a wide range of DoD systems, signal processors that are state-of-the-art when they are fielded rather than when they are first defined. A number of programs are included in the RASSP initiative. This paper introduces the initiative from both technical and programmatic viewpoints.