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Molybdenum disulfide, a two-dimensional material extensively explored for potential applications in non-von Neumann computing technologies, has garnered significant attention owing to the observed hysteresis phenomena in MoS2 FETs. The dominant sources of hysteresis reported include charge trapping at the channel–dielectric interface and the adsorption/desorption of molecules. However, in MoS2 FETs with different channel thicknesses, the specific nature and density of defects contributing to hysteresis remain an intriguing aspect requiring further investigation. This study delves into memristive devices with back-gate modulated channel layers based on CVD-deposited flake-based and thin-film-based MoS2 FETs, with a few-layer (FL) and thin-film (TF) channel thickness. Analysis of current–voltage ( I − V ) and conductance–frequency ( G p / ω − f ) measurements led to the conclusion that the elevated hysteresis observed in TF MoS2 devices, as opposed to FL devices, stems from a substantial contribution from intrinsic defects within the channel volume, surpassing that of interface defects. This study underscores the significance of considering both intrinsic defects within the bulk and the interface defects of the channel when analyzing hysteresis in MoS2 FETs, particularly in TF FETs. The selection between FL and TF MoS2 devices depends on the requirements for memristive applications, considering factors such as hysteresis tolerance and scaling capabilities. [ABSTRACT FROM AUTHOR]

Sufficient energy consumption for conventional information processing makes it necessary to look for new computational methods. One of the possible solutions to this problem is neuromorphic computations using memristive devices. Memristors based on molybdenum disulfide (MoS2$\left(\text{MoS}\right)_{2}$) are a promising way to provide a sizeable amount of hysteresis at low energy costs. Herein, different configurations of MoS2$\left(\text{MoS}\right)_{2}$ memristors as well as the mechanisms involved in hysteresis formation are shown. Bottom gated configuration is beneficial in terms of hysteresis area and energy efficiency. The impact of device channel dimensions on the hysteresis area and energy consumption is discussed. Different operation conditions with triangular, rectangular, sinusoidal, and sawtooth drain‐to‐source pulses are simulated, and rectangular pulses demonstrate the highest energy efficiency. The study shows the potential to realize low‐power neuromorphic systems using MoS2$\left(\text{MoS}\right)_{2}$ memristive devices. [ABSTRACT FROM AUTHOR]

The proposed study demonstrates a single-step CVD method for synthesizing three-dimensional vertical MoS2 nanosheets. The postulated synthesizing approach employs a temperature ramp with a continuous N2 gas flow during the deposition process. The distinctive signals of MoS2 were revealed via Raman spectroscopy study, and the substantial frequency difference in the characteristic signals supported the bulk nature of the synthesized material. Additionally, XRD measurements sustained the material's crystallinity and its 2H-MoS2 nature. The FIB cross-sectional analysis provided information on the origin and evolution of the vertical MoS2 structures and their growth mechanisms. The strain energy produced by the compression between MoS2 islands is assumed to primarily drive the formation of vertical MoS2 nanosheets. In addition, vertical MoS2 structures that emerge from micro fissures (cracks) on individual MoS2 islands were observed and examined. For the evaluation of electrical properties, field-effect transistor structures were fabricated on the synthesized material employing standard semiconductor technology. The lateral back-gated field-effect transistors fabricated on the synthesized material showed an n-type behavior with field-effect mobility of 1.46 cm2 V−1 s−1 and an estimated carrier concentration of 4.5 × 1012 cm−2. Furthermore, the effects of a back-gate voltage bias and channel dimensions on the hysteresis effect of FET devices were investigated and quantified. [ABSTRACT FROM AUTHOR]

In this paper, we introduce analog nonvolatile random access memory cells for neuromorphic computing. The analog memory cell MoS 2 channel is designed based on the simulation model including Fowler–Nordheim tunneling through a charge-trapping stack, trapping process, and transfer characteristics to describe a full write/read circle. 2D channel materials provide scaling to higher densities as well as preeminent modulation of the conductance by the accumulated space charge from the oxide trapping layer. In this paper, the main parameters affecting the distribution of memory states and their total number are considered. The dependence of memory state distribution on channel doping concentration and the number of layers is given. In addition, how the nonlinearity of memory state distribution can be overcome by variation of operating conditions and by applying pulse width modulation to the bottom gate voltage is also shown. [ABSTRACT FROM AUTHOR]

The nonrobotic fabrication of packaged microsystems that contain nonidentical parts has been accomplished by a directed self-assembly process. The self-assembly process uses geometrical shape recognition to identify different components and subsequent bond formation between liquid solder and metal-coated areas to form mechanical and electrical connections. We applied this concept of shape recognition and subsequent formation of contacts to assemble and package microsystems that contained nonidentical subunits. The self-assembly of three-component assemblies is demonstrated by sequentially adding device segments to the assembly solution including 200-[micro]m-sized light-emitting diodes. Six hundred AlGaInP-GaAs light-emitting diode segments self-assembled onto device carriers in 2 min without defects. Encapsulation units self-assembled onto the LED-carrier assemblies to form a three-dimensional (3-D) circuit path to operate the final device. The reported procedure provides a new route to the creation of autonomous heterogeneous microsystems including the realization of autonomous wireless sensor system that requires nonidentical units: CMOS circuitry, Non-CMOS sensor unit for sensing, III-V components for communication, and encapsulation units to form 3-D electrical interconnects. The creation of such systems is being discussed and a proof of concept experiment is being demonstrated. [1563] Index Terms--Heterogeneous integration, sensor systems, sequential self-assembly, solder- and shape-directed self-assembly.

This paper reports on a programmable reconfigurable self-assembly (PRS) process to enable heterogeneous integration of components on nonplanar substrates. The proposed process makes use of solder-based receptors that can be activated electrically. Metal contacts on segmented semiconductor devices bind to liquid-solder-based-receptors on a substrate during the fluidic self-assembly. Programmability is implemented using solder-based receptors that can be switched 'ON' and 'OFF' using integrated heaters. We have evaluated the feasibility of the proposed PRS concept through computer simulations using ANSYS to estimate: i) the necessary power to heat selected receptors to above the melting point of the solder and ii) the minimal spacing between receptors for preventing thermal crosstalk. A prototype platform has been fabricated to experimentally test the PRS process. The programmable sequential assembly of multiple types of components onto target positions has been demonstrated, including 300-[micro]m-sized light-emitting diodes (LEDs) and silicon dies. Three types of defects were identified and eliminated using improved component designs, transient heating, and adequate heat sinks. A prototype color LED display segment that contains a total of 36 red, green, and yellow LED segments and 72 interconnects has been used to test the concept. The outlined process provides a new concept to the parallel integration of micro-devices and systems that require electrical interconnects between components. [1564] Index Terms--Directed assembly, heterogeneous integration, programmable microelectromechanical systems (MEMS), reconfigurable self-assembly, sequential self-assembly, solder-based receptor, template assembly.