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Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

The general theory of conduction in a piezoresistive material subjected to temperature change is derived and the basic equations needed to design and apply test chips for thermal stress measurement are established. A general expression is obtained for the resistance changes which occur in an arbitrarily oriented 1D filamentary conductor subjected to general 3D stress states and arbitrary temperature changes. The derived formula is valid for crystals such as silicon which have cubic symmetry and diamond lattice structures. Basic equations are presented for the resistance changes experienced by stressed in-plane resistors fabricated on (100) silicon wafers. The established theory is applied to a simple two-element sensor rosette. A test chip containing this rosette configuration is designed and fabricated, and a suitable calibration system is constructed.