380 results on '"Jammy, R."'
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2. Fabrication of Superconducting Joints for Ag-Clad BSCCO Conductors
3. Advances in Fabrication of Mono- and Multifilament Ag-Clad BSCCO Superconductors
4. Fabrication and Properties of Silver and Silver-Sheathed BSCCO Conductors
5. Grain boundary-driven leakage path formation in HfO2 dielectrics
6. Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor
7. Processing and Properties of Long Lengths of Ag-Clad BSCCO Superconductors and High-Tc Magnets
8. Effects of parasitics and interface traps on ballistic nanowire FET in the ultimate quantum capacitance limit
9. Gate-first integration of tunable work function metal gates of different thicknesses into high- k/metal gates CMOS FinFETs for multi-Vth engineering
10. Interrelationship between electrical and physical properties of subcritical Si-Ge layers grown directly on silicon for short channel high-performance pMOSFETs
11. Analyzing noise in modern MOSFETs
12. Advances in processing and characterizing Bi-based superconductors
13. Superconducting joints for silver-clad BSCCO tapes
14. Recent issues in fabrication of Ag-clad BSCCO superconductors
15. Processing and characterization of Ag-clad Bi-2223 superconductors
16. Single-crystal Pb(ZrxTi(sub 1-x))O3 thin films prepared by metal-organic chemical vapor deposition: systematic compositional variation of electronic and optical properties
17. Advances in Fabrication of Mono- and Multifilament Ag-Clad BSCCO Superconductors
18. Fabrication of Superconducting Joints for Ag-Clad BSCCO Conductors
19. X-Ray Reflectometry Determination of Structural Information from Atomic Layer Deposition Nanometer-Scale Hafnium Oxide Thin Films
20. A Comparison of Electrical and Physical Properties of MOCVD Hafnium Silicate Thin Films Deposited using Various Silicon Precursors
21. Dipole Model Explaining High-k/Metal Gate Threshold Voltage Tuning
22. Recent advances in bismuth-based superconductors
23. Strain-enhanced scaling of HK+MG CMOSFETs
24. Processing and properties of long-lengths of Ag-clad BSCCO superconductors and high-{Tc} magnets
25. Improvement of metal gate/high-k dielectric CMOSFETs characteristics by atomic layer etching of high-k gate dielectric
26. A Comparative NBTI Study of HfO(2), HfSiO(x), and SiON p-MOSFETs Using UF-OTF I(DLIN) Technique
27. A Novel Fluorine Incorporated Band Engineered (BE) Tunnel (SiO2/ HfSiO/ SiO2) TANOS with Excellent Program/Erase & Endurance to 10^5 Cycles
28. Defect metrology of epitaxial Ge on patterned Si wafers using an inline HRXRD tool
29. Epitaxial systems engineered for tunnel diodes and tunnel FETs
30. Benchmarking and improving III-V Esaki diode performance with a record 2.2 MA/cm2 peak current density to enhance TFET drive current
31. SILICON FINFETS AS DETECTORS OF TERAHERTZ AND SUB-TERAHERTZ RADIATION
32. CONNECTING ELECTRICAL AND STRUCTURAL DIELECTRIC CHARACTERISTICS
33. A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer
34. Effect of ALD oxidant and channel doping on positive bias stress characteristics of surface channel In0.53Ga0.47As nMOSFETs
35. Sub-10nm junction in InGaAs with sulfur mono-layer doping
36. Microscopic model for the kinetics of the reset process in HfO2 RRAM
37. (Invited) Non Planar Non Si CMOS - Challenges and Opportunities
38. Real-time study of switching kinetics in integrated 1T/ HfOx 1R RRAM: Intrinsic tunability of set/reset voltage and trade-off with switching time
39. Effective Schottky Barrier Height modulation using dielectric dipoles for source/drain specific contact resistivity improvement
40. ETB-QW InAs MOSFET with scaled body for improved electrostatics
41. Benchmarking and improving III-V Esaki diode performance with a record 2.2 MA/cm2 peak current density to enhance TFET drive current
42. InAs quantum-well MOSFET (Lg = 100 nm) with record high gm, fT and fmax
43. FinFET parasitic resistance reduction by segregating shallow Sb, Ge and As implants at the silicide interface
44. Hot Forming to Improve Memory Window and Uniformity of Low-Power HfOx-Based RRAMs
45. Conformal, low-damage shallow junction technology (Xj∼5nm) with optimized contacts for FinFETs as a Solution Beyond 14nm Node
46. Emerging CMOS and beyond CMOS technologies for an ultra-low power 3D world
47. (Invited) Integration Challenges of III-V Materials in Advanced CMOS Logic
48. Performance and variability in multi-VT FinFETs using fin doping
49. Simple FinFET gate doping technique for dipole-engineered Vt tuning and CET scaling
50. III–V gate stack interface improvement to enable high mobility 11nm node CMOS
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