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Most of the reduced switch multilevel inverters (MLIs), including switched capacitor MLIs (SC-MLIs), are designed with voltage sources/capacitors have obtained voltage levels with the addition of these sources only. This increases the number of voltage sources (capacitors) without full utilisation of these sources and has higher inverter total standing voltages, which leads the inverter inefficient (high conduction loss) and costly. The motivation of this work is to design a generalised reduced component MLI aiming for addition as well as subtraction of the voltage sources to obtain a voltage level, which results in the reduction of sources, enhance the voltage utilisation and lowering the inverter total standing voltage (TSV). The design parameters of the proposed MLI topology are compared with the recently developed MLIs in terms of the number of switches, capacitors and TSV to prove its superiority. The experimental prototype of the specimen 15-level and 27-level inverters is implemented using DS1103 and the corresponding results are presented. [ABSTRACT FROM AUTHOR]

The maximum power point tracking concept is essential in PV systems to increase the power transfer capability and efficiency. The conventional methods to track maximum power point perform satisfactorily only under uniform solar irradiation, however under partially shaded conditions, PV array offers several local maxima along with one global maximum power transfer point on the P-V curve. This makes optimal tracking more difficult. This paper proposed an improved adaptive MPPT algorithm with varying step size to track the Global Maximum Power Point (GMPP) under different partial shaded conditions. First, the simulation model has been analyzed which is suitable for partially shaded conditions and then the proposed Variable Step-size Adaptive Maximum Power Point Tracking (VSAMPPT) method has been developed to track the global optimal power point for various irradiations. Here changing the duty cycle is not with fixed step size but with variable step size (Dstep), which depends on the square of the difference between the ratio of voltages to current and makes the proposed algorithm faster. The proposed algorithm keeps on adjusting its tracking strategy to find Global Peak Area (GPA) where the global maximum power point can be tracked down very easily. The proposed algorithm has been validated in the laboratory with dSPACE (DS1103) and tested with different case studies. The results demonstrate the effectiveness of the proposed concept over the existing MPPT methods like P&O method, Incremental Conductance (IC), and Adaptive MPPT methods in terms of speed of tracking global maximum power point, accuracy, and flexibility. [ABSTRACT FROM AUTHOR]

In this paper, the generalized and new cascaded modular multilevel inverter topology is presented that is designed with reduced power electronic components. Each module comprises ten power switches (2 bi-directional and 8 unidirectional) and five DC sources. Lower voltage rating switches are employed for this topology due to its remarkable advantage of generating both positive and negative voltage levels without using any H-bridge at the output. Various DC voltage magnitude or MLI algorithm of the proposed topology can be selected to obtain different voltage levels. The most optimal inverter algorithm is selected and further design a generalized cascaded structure for high voltage applications that requires lesser components and has better performance. The performance of the proposed optimal algorithm is determined and are compared with the various other state-of-art MLI topologies. The specimen 27-level inverter of the proposed configuration is modulated using the sinusoidal-PWM (SPWM) technique and is implemented in the laboratory prototype of the experimental setup using a d-SPACE 1103 controller. The performance parameters of the proposed topology stand better than other existing and compared MLI topologies in terms of the variety of DC sources, number of DC sources, number of voltage levels, and number of driver circuits. Regarding the economic reliability of the proposed inverter, total standing voltage (TSV), cost factor per level (CFL) have also been calculated. The experimental results of the 27-level output voltage at different load verify its performance. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) have become more popular due to the high-quality output waveform with higher voltage levels, lower voltage stress across the power switches, and lower harmonic distortion of the output voltage. This paper introduces two new structures of MLI based on a modified T-type inverter and switched-diode cell. Proposed inverter topologies cascaded in series due to its generalized structure. Inherent property to generate the negative voltage levels without using any full H-bridge circuit is a key feature of the proposed topology. The merit of the proposed inverter is the reduction in power electronic components, the assessment has been carried out with some recent MLI topologies, and graphs relating to the performance parameters have also been incorporated as well. Besides, total standing voltage (TSV) and the level to switch ratio (LSR) is calculated for further clarification of the proposed inverter, and the parameters are compared with the newly developed MLI topologies. A multi-carrier pulse width modulation strategy (MC-PWM) is adopted for the generation of the switching pulses. [ABSTRACT FROM AUTHOR]

A novel asymmetrical nine-level inverter topology using only six switches along with its generalized structure are presented in this paper. The proposed reduced switch multilevel inverter topology makes use of a lower total standing voltage for a required output voltage as compared to the existing ones. One of the major advantages of the proposed multilevel inverter over other existing topologies is that, the circuit can be extended to a higher-level inverter, by cascading a few proposed inverter modules and can also be extended to the three-phase structure very easily, thereby making the inverter structure simple. In addition to this, the proposed inverter module does not require any additional H-bridge circuit to obtain the negative voltage levels for AC voltage, resulting in reduced voltage stress on the switches. This paper also incorporates an effective technique to determine the total standing voltage as well as the switching and conduction losses of the inverter. The MATLAB/Simulink based proposed nine-level as well as an 81-level inverters are modeled and the simulation results are presented. An experimental prototype of nine-level inverter using six switches is developed and tested to validate the simulation results. [ABSTRACT FROM AUTHOR]

In this paper a modified space vector pulse-width modulation (SVPWM) technique for a three-phase T-type inverter is pro- posed that utilizes the state redundancies for fault-tolerant ap- plication. The performance of the T-type, 3-level inverter is analyzed with a three-phase induction motor load under the open-circuit fault condition of the inverter. The voltage space vectors of the three-level inverter under the open switch fault (open circuit fault) condition in any one leg of the three-phase inverter is analyzed and modified using the SVPWM adopted to overcome the problems of sudden stall at open switch fault conditions. Modelling and simulation of T-type 3-level inverter using proposed modified space vector pulse width modulation is carried out in the MATLAB/SIMULINK environment. The experimental results are presented here for verification of the simulation results using real-time simulator (dSPACE 1103). [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) emerged as a boon to the industries due to the fact that it fulfils different industrial aspects such as reduced electromagnetic interference, lower maintenance, less installation area and reduced harmonic content. MLI generates a staircase output voltage with suitable combination of power devices and DC voltage sources. In this work, a generalized cascaded MLI is proposed that employs only a half-bridge converter rather than the full H-bridge converter for the polarity-reversal (on which the maximum DC link voltage appears) and thereby also reduces the required number of power switches. Five different types of algorithm in the proposed configuration have been studied and the most optimal algorithm is further elaborated and implemented. A specimen 7-level inverter of the proposed configuration is modeled in MATLAB/Simulink and is further implemented in the laboratory using the controller DS1103. The experimental results for different modulation indices are further amalgamated and verified with the simulation results. Nevertheless, a comparative assessment of different performance-related parameters of the proposed topology along with the generalized expressions is carried out and are also compared with some of the recently published MLI topologies. [ABSTRACT FROM AUTHOR]

Reduction in the overall power devices such as power semi-conductor switches, gate drivers with the associated circuits and DC voltage sources reduces the size, cost, complexity in addition with enhancing the overall performance of the inverter. This paper presents a new and generalized multilevel inverter topology with reduced number of power components. To identify the significance of proposed inverter, the generalized formulae for all the parameters are calculated and a comprehensive comparison of different performance parameters are presented in tabular as well as in graphical form. Multicarrier pulse width modulation strategy is adopted for generating the switching pulses. Simulation of the proposed MLI topology for the 9-level and 17-level inverter have been performed in MATLAB/Simulink and the corresponding experimental results are incorporated for one unit and two units, respectively, experiments are carried out at RL load. Nevertheless, level per switch Ratio (L/S) is introduced and compared with some of the new discussed MLI topologies. Moreover, the switching and the conduction losses of the inverter are also calculated and incorporated in this paper. [ABSTRACT FROM AUTHOR]