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9 results on '"Javerliac, Virgile"'

2. Beyond MRAM, CMOS/MTJ integration for logic components

Author

Prenat, Guillaume, Dieny, Bernard, Guo, Wei, Baraji, Mourad El, Javerliac, Virgile, and Nozieres, Jean-Pierre

Subjects
Memory (Computers), Semiconductor industry, Complementary metal oxide semiconductors, Semiconductor memory, Semiconductor industry, Business, Electronics, Electronics and electrical industries
Published
2009

3. Hybrid STT/CMOS design of an interrupt based instant on/off mechanism for low-power SoC

Author

Layer, Christophe, Jabeur, Kotb, Becker, Laurent, Javerliac, Virgile, Paoli, Pierre, BERNARD-GRANGER, Fabrice, Dieny, Bernard, Gros, Stéphane, Bernard-Granger, Bernard, SPINtronique et TEchnologie des Composants (SPINTEC), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), eVaderis, Minatec, Département d'Architectures, Conception et Logiciels Embarqués-LIST (DACLE-LIST), Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA))

Subjects
non-volatile memory, Magnetoresistive random-access memory, business.industry, Computer science, hybrid magne- tic-CMOS, STT-MRAM, External memory interface, [SPI.TRON]Engineering Sciences [physics]/Electronics, Non-volatile memory, [SPI]Engineering Sciences [physics], Embedded system, Computer data storage, [PHYS.COND.CM-MS]Physics [physics]/Condensed Matter [cond-mat]/Materials Science [cond-mat.mtrl-sci], check-pointing interrupt, System on a chip, low-power system-on-chip, Interrupt, business, Interrupt request, Volatile memory
Abstract

International audience; This paper describes the design and the evaluation of a low-power System-on-Chip (SoC) in an advanced hybrid 40nm magnetic/CMOS technology node. Without external memory interface, the processor of the SoC benefits from a privileged access to the embedded NVM (Non-Volatile Memory), providing means for internal data storage and integrity thanks to its inherent non-volatility. Furthermore, a method based on an IRQ (Interrupt Request) controls the instant-on/off features of the SoC at assembler level through the use of NVM elements and improves the whole system in terms of power consumption and functionality enhancements, compared to an equivalent system relying on standard volatile memory blocks only. We discuss our simulation results on the basis of still image compression benchmarks at various data throughputs and show the benefits of NVM even for rather computation intensive algorithms.

Published
2015

4. Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories

Author

Layer, Christophe, primary, Becker, Laurent, additional, Jabeur, Kotb, additional, Claireux, Sylvain, additional, Dieny, Bernard, additional, Prenat, Guillaume, additional, Pendina, Gregory Di, additional, Gros, Stephane, additional, Paoli, Pierre, additional, Javerliac, Virgile, additional, Bernard-Granger, Fabrice, additional, and Decloedt, Loic, additional

Published
2016
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8. CMOS/Magnetic Hybrid Architectures

Author

Prenat, Guillaume, primary, El Baraji, Mourad, additional, Guo, Wei, additional, Sousa, Ricardo, additional, Javerliac, Virgile, additional, Nozieres, Jean-Pierre, additional, Zhao, Weisheng, additional, and Belhaire, Eric, additional

Published
2007
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9. High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits.

Author

Weisheng Zhao, Chappert, Claude, Javerliac, Virgile, and Nozière, Jean-Pierre

Subjects
TUNNELS, LOGIC circuits, MICROELECTRONICS, MAGNETIC properties, TRANSISTORS, ELECTRONIC circuits
Abstract

Densely embedding Magnetic Tunnel Junctions (MTJ) in CMOS logic circuits is considered as one potentially powerful solution to bring non volatility, instant on/off and low standby power in today's programmable logic circuits, in order to overcome major drawbacks while preserving high operation speed. A critical issue in this process is the integration of MTJ electric signal to CMOS electronics, in particular the requirement of "zero" read/write error for logic applications. In this paper, we propose a new sense amplifier circuit, called Pre-Charge Sense Amplifier (PCSA). This circuit, comprising 7 CMOS transistors at minimum size, is able to read the magnetic configuration of a pair of magnetic tunnel junctions with opposite configurations at high speed (about 200 ps), with very low power and error rate compared to previously proposed solutions. Simulations using a ST Microelectronics 90 nm design kit and a compact model of MTJ demonstrate the performances of PCSA. [ABSTRACT FROM AUTHOR]

Published
2009
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