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Optoelectronic devices based on layered two-dimensional (2D) van der Waals (vdW) semiconductors and their heterostructures suffer from carrier scattering, trapping, and trap-assisted recombination-generation at the vdW channel/dielectric interface. In this work, we demonstrate improved photoresponse of a dielectric-free, suspended WSe2 (p)-ReS2 (n) heterostructure photodetector in comparison to an hBN dielectric-supported structure fabricated over a common local Au back gate. The dielectric-free suspension helps in eliminating optical losses at the 2D channel–dielectric interface and optical absorption loss in the dielectric itself as the metal (gold) gate aids in reflecting the incident light to enhance absorption in the 2D heterostructure. The increase in photocurrent increases with incident illumination power and is consistent over a wide range of wavelengths. Suspension of 2D layered materials, thus, paves the route for harnessing their intrinsic properties for next generation photodetection applications. [ABSTRACT FROM AUTHOR]

Layered 2D van der Waals semiconductors and their heterostructures have been shown to exhibit positive photoconductance (PPC) in many studies. A few recent reports have demonstrated negative photoconductance (NPC) as well that can enable broadband photodetection besides multi‐level optoelectronic logic and memory. Controllable and reversible switching between PPC and NPC is a key requirement for these applications. This report demonstrates visible‐to‐near infrared wavelength‐driven NPC and PPC, along with reversible switching between the two, in an air stable, high mobility, broadband black phosphorus field effect transistor covered with a few layer MoS2 flake. The crossover switching wavelength can be tuned by varying the MoS2 bandgap through its flake thickness and the NPC and PPC photoresponsivities can be modulated using electrostatic gating as well as laser power. Recombination‐driven NPC and PPC, as supported by density functional theory calculations, allows for reversible switching. Further, gate voltage‐dependent negative persistent photoconductance is well‐suited for optosynaptic applications. [ABSTRACT FROM AUTHOR]

Excellent light-matter interaction and a wide range of thickness-tunable bandgaps in layered vdW materials coupled by the facile fabrication of heterostructures have enabled several avenues for optoelectronic applications. Realization of high photoresponsivity at fast switching speeds is a critical challenge for 2D optoelectronics to enable high-performance photodetection for optical communication. Moving away from conventional type-II heterostructure pn junctions towards a WSe 2 /SnSe 2 type-III configuration, we leverage the steep change in tunneling current along with a light-induced heterointerface band shift to achieve high negative photoresponsivity, while the fast carrier transport under tunneling results in high speed. In addition, the photocurrent can be controllably switched from positive to negative values, with ∼10 4 × enhancement in responsivity, by engineering the band alignment from type-II to type-III using either the drain or the gate bias. This is further reinforced by electric-field dependent interlayer band structure calculations using density functional theory. The high negative responsivity of 2 × 10 4 A/W and fast response time of ∼1 μs coupled with a polarity-tunable photocurrent can lead to the development of next-generation multifunctional optoelectronic devices.

Two-dimensional MoS 2 gas sensors have conventionally relied on a change in field-effect-transistor (FET) channel resistance or in the Schottky contact/pn homojunction barrier. We demonstrate an enhancement in sensitivity (6×) and dynamic response along with a reduction in detection limit (8×) and power (10 4 ×) in a gate-tunable type-II WSe 2 (p)/MoS 2 (n) heterodiode gas sensor over an MoS 2 FET on the same flake. Measurements for varying NO 2 concentration, gate bias, and MoS 2 flake thickness, reinforced with first-principles calculations, indicate dual-mode operation due to (i) a series resistance-based exponential change in the high-bias thermionic current (high sensitivity), and (ii) a heterointerface carrier concentration-based linear change in near-zero-bias interlayer recombination current (low power) resulting in sub-100 μW/cm 2 power consumption. Fast and gate-bias tunable recovery enables an all-electrical, room-temperature dynamic operation. Coupled with the sensing of trinitrotoluene (TNT) molecules down to 80 ppb, this study highlights the potential of the WSe 2 /MoS 2 pn heterojunction as a simple, low-overhead, and versatile chemical-sensing platform.

Clockwise to anticlockwise hysteresis crossover in current-voltage transfer characteristics of field-effect transistors (FETs) with graphene and MoS 2 channels holds significant promise for nonvolatile memory applications. However, such crossovers have been shown to manifest only at high temperature. In this work, for the first time, we demonstrate room temperature hysteresis crossover in few-layer MoS 2 FETs using a gate-drain underlap design to induce a differential response from traps near the MoS 2 -HfO 2 channel-gate dielectric interface, also referred to as border traps, to applied gate bias. The appearance of trap-driven anticlockwise hysteresis at high gate voltages in underlap FETs can be unambiguously attributed to the presence of an underlap since transistors with and without the underlap region were fabricated on the same MoS 2 channel flake. The underlap design also enables room temperature tuning of the anticlockwise hysteresis window (by 140×) as well as the crossover gate voltage (by 2.6×) with applied drain bias and underlap length. Comprehensive measurements of the transfer curves in ambient and vacuum conditions at varying sweep rates and temperatures (RT, 45 °C, and 65 °C) help segregate the quantitative contributions of adsorbates, interface traps, and bulk HfO 2 traps to the clockwise and anticlockwise hysteresis.

Few-layer black phosphorus (BP) has attracted significant interest in recent years due to electrical and photonic properties that are far superior to those of other two-dimensional layered semiconductors. The study of long term electrical stability and reliability of black phosphorus field effect transistors (BP-FETs) with technologically relevant thin, and device-selective, gate dielectrics, stressed under realistic (closer to operation) bias and measured using state-of-the-art ultrafast reliability characterization techniques, is essential for their qualification and use in different applications. In this work, air-stable BP-FETs with a thin top-gated dielectric (15 nm Al 2 O 3 , SiO 2 equivalent thickness of 5 nm) were fabricated and comprehensively characterized for threshold voltage ( V th ) instability under negative gate bias stress at various measurement delays ( t m ), stress biases ( V GSTR ), temperatures ( T), and stress times ( t str ) for the first time. Thin top-gated oxide enables low V GSTR that is closer to the operating condition and ultrafast V th measurements with low delay ( t m = 10 μs, due to high drain current) that ensure minimal recovery. The resultant time kinetics of V th degradation (Δ V th ) shows fast saturation at longer stress times and low-temperature activation energy. V th instability in these top-gated devices is suggested to be dominated by hole trapping, which is modeled using first-order equations at different V GSTR and T. It is shown that measurements using larger t m show lower degradation magnitude that do not saturate due to recovery artifacts and give inaccurate estimation of hole trap densities. Conventional, thick, and global back-gated oxide BP-FETs were also fabricated and characterized for varying t m (1 ms being the lowest due to a low drain current level for thick oxide), V GSTR , and T to benchmark our top-gated results. Nonsaturating Δ V th in the back-gated devices is shown to result from recovery artifacts due to the large t m (1 ms and greater) values. Finally, using a V GSTR and T-dependent first-order model, we show that the top-gated Al 2 O 3 BP-FETs with scaled gate oxide thickness can match state-of-the-art Si reliability specifications at operating voltage and room/elevated temperature.