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This article presents a discrete-time $\Delta \Sigma $ modulator (DSM) with a wide linear input range and high input impedance for biomedical signal acquisition. The proposed integrated circuit (IC) is based on a 1st-order DSM with 2nd-order noise-shaping (NS)-successive approximation (SAR) for high resolution with high power efficiency, directly converting the small input signal to digital. The first-stage integrator in the DSM is designed to support not only for wide-input swing at low power consumption but also for high input impedance. The input impedance is further boosted by a proposed presampling-based charge-transfer-reduction technique, which does not require any additional amplifiers. It precharges the sampling capacitor with just the previous sampled signal, thus reducing the charge transfer and boosting the input impedance. Besides, we also propose a new truncation-error shaping method. By feeding the truncation error back to the local NS-SAR loop, the truncation error is effectively noise-shaped without using any additional loop, resulting in 4th-order NS. The prototype IC is fabricated in a 65-nm CMOS process. It achieves 94.5-dB signal-to-noise-and-distortion ratio (SNDR) for 1–500-Hz bandwidth with 600-mVPP input applied, resulting in FoMSNDR of 174.3 dB and FoMDR of 175.8 dB. It achieves over 83-dB common-mode rejection ratio (CMRR) and input impedance of 208 $\text{M}\Omega $ at dc and 31.5 $\text{M}\Omega $ at the target bandwidth. Moreover, its artifact tolerance is verified by in vitro and in vivo measurements.

This review article provides a comprehensive overview of impedance-readout integrated circuits (ICs) for electrical impedance spectroscopy (EIS) applications. The readout IC, a crucial component of on-chip EIS systems, significantly affects key performance metrics of the entire system, such as frequency range, power consumption, accuracy, detection range, and throughput. With the growing demand for portable, wearable, and implantable EIS systems in the Internet-of-Things (IoT) era, achieving high energy efficiency while maintaining a wide frequency range, high accuracy, wide dynamic range, and high throughput has become a focus of research. Furthermore, to enhance the miniaturization and convenience of EIS systems, many emerging systems utilize two-electrode or dry electrode configurations instead of the conventional four-electrode configuration with wet electrodes for impedance measurement. In response to these trends, various technologies have been developed to ensure reliable operations even at two- or dry-electrode interfaces. This article reviews the principles, advantages, and disadvantages of techniques employed in state-of-the-art impedance-readout ICs, aiming to achieve high energy efficiency, wide frequency range, high accuracy, wide dynamic range, low noise, high throughput, and/or high input impedance. The thorough review of these advancements will provide valuable insights into the future development of impedance-readout ICs and systems for IoT and biomedical applications.

The escalating demand for high-resolution sensor interface systems, driven by the proliferation of the Internet of Things (IoT) and wearable smart devices, has led to the widespread use of capacitive sensing transducers. These transducers are valued for their low-noise and low-power characteristics, making them suitable for various applications, including environmental and biomedical sensing. However, designing a high-resolution capacitive sensor interface system while maintaining power efficiency remains challenging. This article proposes a high-resolution energy-efficient highpass (HP) $\Delta \Sigma $ capacitance-to-digital converter (CDC) architecture. The architecture incorporates a 2nd-order HP $\Delta \Sigma $ modulator ( $\Delta \Sigma \text{M}$ ) and a continuous-time capacitance-to-voltage converter (CT CVC). The proposed CDC achieves an excellent capacitance resolution of 5.85 aFrms, with a power efficiency of 46 fJ/conversion-step and an FoMS of 187.4 dB. The HP $\Delta \Sigma \text{M}$ , designed with superior power efficiency, offers a promising solution for high-resolution capacitive sensor applications. Compared to state-of-the-art, the proposed CDC achieves more than 2 $\times $ FoMS improvement while maintaining competitive FoMW.