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5. Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization

10. Machine Learning-Based Read Access Yield Estimation and Design Optimization for High-Density SRAM

19. 24.3 A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology

27. Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving.

43. Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region.

44. Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation.

45. Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory.

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