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Bitline (BL) charge-recycling-based static random access memory (SRAM) write assist circuits (BCR-WA) are proposed to reduce the minimum operating voltage ($V_{\mathrm {MIN}}$) of SRAM. In the proposed schemes, the charges stored on the unselected BL are utilized to raise the cell ground voltage (VSS) of the selected bit cell, and the increased cell VSS (CVSS) enhances the write ability. According to the metal routing direction of CVSS in the layout, two types of BCR-WA are proposed, BCR-WA for vertical CVSS routing (BCR-WA $_{\mathrm {V}}$) and horizontal CVSS routing (BCR-WA $_{\mathrm {H}}$). To evaluate the proposed circuits, HSPICE simulations are performed and the test chip is implemented using a 14-nm FinFET technology. Thanks to the charge-recycling operation, BCR-WAV and BCR-WAH can save energy by 11%–44% and 30%–66%, respectively, compared to the previous write assist circuits, with a comparable or less area overhead and an insignificant degradation in read performance (<1%) and stability (~25-mV degradation in maximum word-lin voltage). In addition, according to simulation results, BCR-WAV and BCR-WAH can lower $V_{\mathrm {MIN}}$ by 150 mV. In particular, silicon measurement result for BCR-WAH proves an 125-mV improvement in $V_{\mathrm {MIN}}$. [ABSTRACT FROM AUTHOR]

A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage ( $V_{{\rm {th}}})$ region, where the supply voltage ( $V_{{\rm {DD}}})$ is slightly higher than $V_{{\rm {th}}}$ . When $V_{{\rm {DD}}}$ is scaled down to near $V_{{\rm {th}}}$ , the drain current becomes greatly sensitive to $V_{{\rm {DD}}}$ or $V_{{\rm {th}}}$ ; furthermore, the energy exhibits the same sensitivity as that in the super- $V_{{\rm {th}}}$ region. The conventional FOM, the energy-delay product (EDP), is not applicable in the near- $V_{{\rm {th}}}$ region, because the EDP does not consider the sensitivity difference between the energy and the delay. The procedure for establishing an FOM that can appropriately consider the sensitivity difference by fitting the characteristics of a transistor is first introduced. Then, the FOM developed by the proposed procedure is applied to the examples of an inverter chain operating in both the super- $V_{{\rm {th}}}$ and near- $V_{{\rm {th}}}$ regions, which verifies that the proposed FOM is appropriate in the near- $V_{{\rm {th}}}$ region, whereas the EDP is not. [ABSTRACT FROM AUTHOR]

A near-threshold voltage ( $V_{{\rm {th}}}$ ) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super- $V_{{\rm {th}}}$ operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near- $V_{{\rm {th}}}$ region. The recently proposed SRAM bit-cell s with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near- $V_{{\rm {th}}}$ region. This paper proposes a read buffer with adjusted the number of fins or $V_{{\rm {th}}}$ to resolve the problems in the near- $V_{{\rm {th}}}$ region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near- $V_{{\rm {th}}}$ region. [ABSTRACT FROM AUTHOR]

We prove analytically that the yield of static random access memory (SRAM) is intrinsically a function of its architecture owing to the correlation among cell failures. In addition, architecture-aware analytical yield models are proposed for read access. The yield results using the proposed models show that the most dominant factor determining yield is the variation in the voltage difference between bitlines due to the cell leakage current variation according to the SRAM architecture. The models also show the possibility that the most dominant factor determining the yield can change with the relative ratios among the amounts of changes in the correlation, recovery sample space, distributions of the sense amplifier enable time, voltage difference between bitlines, as well as sense amplifier offset voltage, memory capacity, and redundancy scheme. The proposed yield models show that combined row and column redundancy ensures the highest yield, whereas column redundancy is the most efficient. [ABSTRACT FROM AUTHOR]