Search

A major challenge facing diamond electronics is creating reliable and stable ohmic contacts to a hydrogen-terminated diamond (D:H) conducting surface. In this work, we explore a novel contact-first approach for creating refractory, scalable, and self-aligned ohmic contacts to D:H. Our contacts are based on W sputtered on O-terminated diamond followed by surface hydrogenation. We show that the H-plasma treatment provides a suitable thermal step to create the ohmic contact that relies on the formation of WC at the diamond surface. This thermal step also causes an order of magnitude increase in the W sheet resistance though the metallization that remains mechanically stable. The best contact resistance obtained in this work is $2.6~\Omega $ -mm. We further demonstrate that the electrical contact takes place exclusively at the edge of the metal.

In the presence of prominent gate oxide trapping, the conventional technique for channel mobility extraction in MOSFETs based on ${I}$ – ${V}/{C}$ – ${V}$ measurements becomes inadequate. This is the consequence of two different effects associated with oxide traps: gate voltage stretch-out and electron trapping and detrapping in the oxide at the megahertz (MHz)-range frequencies that are commonly utilized. In thin-channel planar InGaAs MOSFETs, both effects are observed and found to result in a severe overestimation of mobile charge and subsequently an underestimation of mobility using ${I}$ – ${V}/{C}$ – ${V}$ . To address this issue, we demonstrate a new mobility extraction technique (RF- ${I}_{D}$ ) based on concurrent ${I}$ – ${V}$ and ${S}$ -parameter measurement in the gigahertz (GHz) regime that is largely immune to oxide trapping. Excellent agreement with Hall measurements as well as with theoretical predictions from Poisson–Schrodinger simulations gives confidence to the new technique. Importantly, the new technique is not limited to InGaAs planar MOSFETs, but applies to any device geometry and any material system. Promising mobility ~1100 cm2/ $\text{V}\cdot \text{s}$ is found in quantum-well planar InGaAs MOSFETs with a 4-nm-thick channel.

In this article, a detailed simulation study of high-performance InGaAs quantum-well (QW) MOSFETs is presented. We demonstrate that the limited free carrier density in the access region leads to a significant source starvation effect in the saturation regime, which limits the maximum transconductance ( ${g}_{m}$ ). By coupling ballistic 2-D quantum mechanical simulations with an original semiclassical model for source starvation, we are able to reproduce quantitatively the ${V}_{\text {GS}}$ – ${g}_{m}$ characteristics of three successive device generations differing only in the design of their access region. Source starvation is approximated as a quasi-equilibrium phenomenon characterized by a nonlinear, current-dependent voltage drop in the access region that reduces injection into the channel at high currents. Even in the most recent record device with a ${g}_{m}$ peak of 3.45 mS/ $\mu \text{m}$ , source starvation is found to have a negative impact. An extrapolation of our model furthermore suggests that source starvation will become a major performance bottleneck in future device realizations with lower trap densities.

GaN electronics constitutes a revolutionary technology with power handling capabilities that amply exceed those of Si and other semiconductors in many applications. RF, microwave, and millimeter-wave GaN-based power amplifiers are now deployed in commercial communications, radar, and sensing systems. GaN power transistors for electrical power management are also starting to reach the marketplace. From the dawn of this technology, inadequate transistor stability and reliability have represented stumbling blocks preventing widespread commercial use of GaN electronics. Intense research has been devoted to addressing these issues, and great progress has taken place recently. This article reviews some of the most interesting and significant stability and reliability issues that have plagued GaN power field-effect transistors for RF and power management applications.

We study the impact of fin-width scaling on transport in highly doped InGaAs fins and the effect of digital etch (DE). Our experiments suggest the existence of a 10-nm-wide “deadzone” on each side of the fin that does not contribute to the transport. The extent of the deadzone cannot be mitigated by DE nor sidewall passivation. Simulations suggest that the Fermi-level pinning and its associated subsurface depletion region alone cannot explain the relatively wide deadzone that is measured. We propose an explanation based on the combination of Fermi-level pinning and mobility degradation as the fin width scales down. This leads to an apparent wider deadzone than accounted by the Fermi-level pinning alone.

InGaAs FinFETs are challenged by relatively high leakage current in the OFF state. This originates from band-to-band tunneling (BTBT) at the drain end of the channel that is amplified by a parasitic bipolar effect (PBE) as a result of its floating body. In this paper, we present a simple model of the PBE in InGaAs FinFETs, which captures the key gate length and fin width dependences. Our model accounts for surface recombination at the sidewalls of the fin as well as bulk recombination at the heavily doped source. When compared with experimental results, our model suggests that fin sidewall recombination dominates in long gate length transistors and leads to an exponential gate length dependence of the current gain on the parasitic bipolar junction transistor (BJT). The model enables the extraction of the carrier diffusion length which exhibits the predicted fin width dependence. For short gate length transistors, source recombination is shown to dominate and the parasitic bipolar gain scales with the inverse of the gate length.

We experimentally demonstrate a new paradigm for monolithic three-dimensional (3D) integration: X3D, which enables a wide range of semiconductors - including silicon (Si), III-V, and nanotechnologies such as carbon nanotubes (CNTs) - to be heterogeneously integrated together in monolithic 3D integrated systems. Such flexible heterogeneous integration has potential for a wide range of applications, as each layer of monolithic X3D integrated circuits (ICs) can be customized for specific functionality (e.g., wide-bandgap III-V-based circuits for power management, CNT field-effect transistors (CNFETs) for energy-efficient computing, and tailored materials for custom sensors or imagers). As a case study, we experimentally demonstrate monolithic X3D ICs with five vertical circuit layers heterogeneously integrating three different semiconductors: Si junctionless nanowire field-effect transistors (JNFETs), III-V JNFETs, and CNFETs (also junctionless). The layers of monolithic X3D IC are, from bottom-to-top: Si p-JNFETs, n-CNFETs, Si n-JNFETs, p-CNFETs, and III-V n-JNFETs. Each layer is fabricated using an identical process flow for ease of integration. Importantly, we show that circuits fabricated on each vertical layer are agnostic to subsequent monolithic X3D processing, experimentally demonstrating ability to interleave these “X” (arbitrary) semiconductors in arbitrary vertical ordering. As a final demonstration, we fabricate complementary digital logic circuits comprising different technologies that span multiple vertical circuit layers. This work demonstrates a new paradigm for ICs, allowing for flexible and customizable electronic systems.

This work presents an experimental study of ballistic transport parameters of nanometer-scale InGaAs FinFETs with fin widths down to 9 nm. In these types of transistors, gate oxide trapping represents a significant confounding factor that leads to severe underestimation of mobility and injection velocity. Using a combination of I-V and S-parameter measurements up to 50 GHz, we extract charge control relationship, mobility and injection velocity in a manner that is immune to oxide trapping. While long-channel mobility is found to degrade in narrower fins, short-channel mobility remains unaffected. This is due to an enhancement in ballistic mobility as fin width narrows. Furthermore, the injection velocity shows no discernable fin width dependence. These results can be explained by channel quantization, as verified by k•p simulations. Importantly, they suggest promising transport characteristics in nanoscale InGaAs FinFET technology, and that long-channel mobility constitutes a poor predictor of short-channel performance of InGaAs FinFETs.

We have carried out a detailed experimental study of the switching dynamics of HfZrO 2 Metal-Ferroelectric-Metal (MFM) and Metal-Ferroelectric-Insulator-Metal (MFIM) structures. In order to extract the intrinsic dynamic response, our experimental methodology has paid close attention to minimizing and calibrating all circuit and sample parasitics. In MFM structures, we have found no evidence of negative capacitance (NC) effect. A new dynamic model based on the multi-domain Preisach model describes well all observed behavior including major and minor charge-voltage loops. Our study also reveals the crucial role that parasitics play in the observed device dynamics and can explain claims of NC effects in MFM structures in the literature. In our MFIM structures, we observe clear NC behavior. We not only confirm the transient quasi-static S-like ferroelectric (FE) charge-field behavior described in the literature, but for the first time, we report a dynamic response that displays a hysteretic behavior in the NC region. A model based on the Landau-Khalatnikov (L-K) equation that incorporates FE dynamics via a phenomenological frictional resistance adequately describes the observed results when that resistance is made dependent on the direction of the voltage drive vs. time. Mitigation of this hysteretic NC behavior will be crucial for the harnessing of NC in practical MOSFETs.

Physical neural networks made of analog resistive switching processors are promising platforms for analog computing. State-of-the-art resistive switches rely on either conductive filament formation or phase change. These processes suffer from poor reproducibility or high energy consumption, respectively. Herein, we demonstrate the behavior of an alternative synapse design that relies on a deterministic charge-controlled mechanism, modulated electrochemically in solid-state. The device operates by shuffling the smallest cation, the proton, in a three-terminal configuration. It has a channel of active material, WO3. A solid proton reservoir layer, PdHx, also serves as the gate terminal. A proton conducting solid electrolyte separates the channel and the reservoir. By protonation/deprotonation, we modulate the electronic conductivity of the channel over seven orders of magnitude, obtaining a continuum of resistance states. Proton intercalation increases the electronic conductivity of WO3 by increasing both the carrier density and mobility. This switching mechanism offers low energy dissipation, good reversibility, and high symmetry in programming., Designing energy efficient neural networks based on synaptic memristor devices remains a challenge. Here, the authors propose the development of a 3-terminal WO3 synaptic device based on proton intercalation in inorganic materials by leveraging a solid proton reservoir layer PdHx as the gate terminal.

A p-type Diamond:H/WO 3 metal-oxide-semiconductor field-effect transistor (MOSFET) based on surface transfer doping is demonstrated. Using a low-temperature ALD-grown HfO 2 as gate insulator, the Diamond:H/WO 3 MOSFETs show excellent output characteristics, gate-controllable 2-D hole gas, and low gate leakage current. Long-channel FETs exhibit improved subthreshold behavior but reduced transconductance with respect to short-channel devices. An observed WO 3 -thickness-dependent threshold voltage is consistent with enhanced surface transfer doping as the WO 3 layer is thinned down. Low-temperature measurements suggest a significantly lower mobility than expected in this material system. This illustrates the challenge of maintaining high TMO quality during device fabrication.

It is my great pleasure to announce the winner of the 2020 Electron Devices Society George E. Smith Award given to a paper published in IEEE Electron Device Letters in 2020. The selection was made by vote of EDL’s Editors. The letter is titled “Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors” and it is authored by Arnout Beckers, Farzan Jazaeri, and Christian Enz, all with the Integrated Circuits Laboratory (ICLAB), Ecole Polytechnique Federale de Lausanne (EPFL), Neuchâtel, Switzerland. The letter was published in the February 2020 issue of EDL.

The electrical degradation of InAlN/GaN high-electron-mobility transistors for millimeter-wave applications has been examined under simultaneous high ${V}_{\text {DS,stress}}$ and high ${I}_{{D\text {stress}}}$ electrical stress. Besides a drain current decrease and a positive threshold voltage shift, the creation of an anomalous source-side gate leakage path has been identified. We attribute this to high electric-field induced trap generation in the AlN layer directly under the gate edge on the source side. The resulting increase in gate leakage further exacerbates the degradation of the gate diode. In addition, we postulate that high-power stress leads to significant device self-heating that causes gate sinking and leads to a permanent positive threshold voltage shift and drain current degradation.

GaN field-effect transistors with impressive power switching characteristics have been demonstrated. Preventing their widespread field deployment are reliability and instability concerns. Some emanate from the use of a dielectric in the gate stack. Under typical operation, the gate dielectric comes periodically under intense electric field. This causes trapping and detrapping of electrons and introduces transient shifts in the threshold voltage, a phenomenon known as Bias-Temperature Instability (BTI). A high electric field also results in the formation of defects inside the dielectric. Over time, the defects accumulate and eventually result in the abrupt creation of a conducting path that shorts the dielectric and renders the device inoperable. This process, known as Time-Dependent Dielectric Breakdown (TDDB), often imposes a maximum lifetime for the FET technology. This article presents a methodology for the study of BTI and TDDB in insulated-gate GaN FETs. Our findings paint a picture of BTI and TDDB that in many respects is similar to that of Si transistors but with some unique characteristics. Understanding the physics and developing appropriate lifetime models is essential to enabling the deployment of this important new power electronics technology.

A tunable wavelength laser system and high-resolution transient capture system are introduced to characterize transients in high-mobility MOSFETs. The experimental configuration enables resolution of fast transient signals and new understanding of charge collection mechanisms. The channel layer is critical in the charge collection process for the InGaAs FinFETs examined here. The transient current mainly comes from the channel current, due to shunt effects and parasitic bipolar effects, instead of the junction collection. The charge amplification factor is found to be as high as 14, which makes this technology relatively sensitive to transient radiation. The peak current is inversely proportional to the device gate length. Simulations show that the parasitic bipolar effect is due to source-to-channel barrier lowering caused by hole accumulation in the source and channel. Charge deposited in the channel causes prompt current, while charge deposited below the channel causes delayed and slow current.

Physics-based transistor models are important for technology projections and circuit simulations. To date, there has been little discussion on the incorporation of ballistic effects in transistor models. Recent experimental studies have revealed the significance of ballistic transport in the electrical characteristics of nanometer-scale InGaAs MOSFETs with ultra-low external resistance. Without proper accounting for the ballistic resistance and its gate voltage dependence, the access resistance to the intrinsic device cannot be accurately determined, and any physics-based transistor modeling is bound to fail. In this letter, we show that the MIT Virtual Source model, which natively captures ballistic transport physics, correctly incorporates the impact of ballistic resistance. As a result, it accurately models the electrical characteristics of self-aligned nanoscale InGaAs MOSFETs, an excellent model system for near-ballistic transistors, over a broad operational range. We also show that the success of the model development effort crucially relies on the correct extraction of the external source and drain resistance, ${R}_{{\text {sd}}}$ , from experimental measurements.

This paper demonstrates InGaAs vertical nanowire (VNW) MOSFETs fabricated via an improved top–down approach, the performance of which is comparable to that of the best bottom–up devices in terms of the balance between transport and electrostatics. These devices, when contrasted with an earlier generation fabricated by a similar technology, have enabled the first experimental study of source/drainasymmetry in InGaAs VNWMOSFETs. The transconductance differs significantly when swapping source and drain due to inherently different top and bottom contact electrical resistance. This also results in distinct asymmetry in the saturation behavior of the output characteristics. On the other hand, diameter nonuniformity along the nanowire (NW) length is responsible for asymmetry in the subthreshold characteristics. A uniform NW cross section, enabled by our improved InGaAs dry etch technology in the present devices, eliminates the asymmetry of the electrostatics, which was observed in our previous work.

This paper is aimed to compare the performance of toroidal inductors and planar spiral inductors in multilayered technologies, in terms of achievable inductance density. The optimization of planar toroidal inductors in multilayered substrates is investigated theoretically, and closed formulae are derived for their inductances as a function of geometrical parameters. The obtained model is validated by experimental results and electromagnetic simulation. From the comparison of the inductance of toroidal inductors and compact spiral inductors, a selection rule is proposed to choose the most suitable topology that leads to the most compact design.

The effects of total-ionizing-dose irradiation are investigated in HfO2/InGaAs quantum-well MOSFETs. Radiation-induced hole trapping is higher for irradiation under positive gate bias than under negative gate bias. Electrical stress-induced electron trapping compensates radiation-induced hole trapping during positive gate-bias irradiation. Stress-induced hole trapping adds to the effects of radiation-induced hole trapping under negative gate bias. Radiation-induced charge trapping increases with the channel length.

Thermal atomic layer etching (ALE) was demonstrated on ternary III-V compound semiconductors. In particular, thermal ALE on InGaAs and InAlAs was achieved with sequential, self-limiting fluorination and ligand-exchange reactions using hydrogen fluoride (HF) as the fluorination reactant and dimethylaluminum chloride (DMAC) as the ligand-exchange reactant. Thermal ALE was investigated on planar surfaces and three-dimensional nanostructures. The measured radial etch rates on In

We study the performance degradation of InGaAs FinFETs as they scale to sub-10 nm fin width. This is often attributed to degradation in intrinsic transport parameters. High frequency measurements, however, indicate increasingly severe oxide trapping as the fin width narrows. This is confirmed by pulsed-IV measurements. A new mobility extraction method using concurrent S-parameter and DC-IV measurements avoids the impact of oxide trapping and reveals promising mobility in thin-channel InGaAs planar MOSFETs and narrow-width FinFETs. Our study suggests that performance degradation of InGaAs FinFETs is largely an extrinsic phenomenon that can be engineered around and that the potential performance of deeply-scaled InGaAs FinFETs is significantly underestimated.

For the first time, thermal atomic layer etching (ALE) on InGaAs-based III-V heterostructures is demonstrated. Also, we report the first transistors fabricated by the thermal ALE technique in any semiconductor system. We further highlight one unique advantage of thermal ALE: its integration with atomic layer deposition (ALD) in a single vacuum chamber. Using in situ ALE-ALD, we have fabricated the most aggressively scaled self-aligned In 0.53 Ga 0.47 As n-channel FinFETs to date, featuring sub-5 nm fin widths. The narrowest FinFET with $\mathrm{W_{f}}=2.5$ nm and $\mathrm{L_{g}} =60$ nm shows $\mathrm{g}_{\mathrm{m}}=0.85\ \text{mS}/\mu \mathrm{m}$ at $\mathrm{V}_{\text{ds}}=0.5$ V. Devices with $\mathrm{W_{f}}=18$ nm and $\mathrm{L_{g}}=60$ nm demonstrate $\mathrm{g_{m}}=1.9\ \ \text{mS}/\mu \mathrm{m}$ at $\mathrm{V}_{\text{ds}}=0.5$ V. Subthreshold swings averaging $\mathrm{S}_{\text{lin}}=70$ mV/dec and $\mathrm{S}_{\text{sat}}=74$ mV/dec across the entire range of W f , at minimum $\mathrm{L_{g}}=60$ nm have been obtained. These are all record results. The transistors demonstrated here show an average 60% gm improvement over devices fabricated through conventional techniques. These results suggest a very high-quality MOS interface obtained by the in situ ALE-ALD process.

IEEE Electron Device Letters is one of the most selective rapid publication venues within the field of electron devices. Our goal is to rapidly publish strictly novel research results that are also highly relevant. Accomplishing this goal would not be possible without the strong support of the technical professionals—authors and reviewers from academic, industrial, and government institutions worldwide—who directly contribute to the content and quality of this journal.

We study the scaling properties of self-aligned InGaAs FinFETs with sub-10-nm fin widths fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5, and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices feature self-aligned metal contacts that are 20–30 nm away from the edge of the gate. FinFETs with $L_{g}=30$ nm, $W_{f}=7$ nm, and channel height of 40 nm exhibit a transconductance of $900~\mu \text{S}/\mu \text{m}$ at $V_{\mathrm { {DS}}}=0.5$ V. When normalized to $W_{f}$ , this is a record value among all III–V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls.

The degradation of InAlN/GaN high-electron-mobility transistors (HEMTs) for millimeter-wave applications has been examined under on conditions. Two dominant permanent degradation mechanisms have been identified as well as two trapping mechanisms which affect the device characteristics in different ways. Under high-voltage, low-current stress conditions, we have observed permanent enhancement in the maximum drain current $I_{D\mathrm {{max}}}$ that arises from a negative shift in threshold voltage $V_{T}$ . We attribute this mechanism to depassivation of hydrogenated defects. Under the same stress conditions, there is prominent and reversible hot-electron trapping on the drain side of the device that brings $I_{D\mathrm {{max}}}$ down and increases the drain resistance. Under low-voltage high-current stress conditions, there is a visible permanent reduction in $I_{D\mathrm {{max}}}$ and a positive shift in $V_{T}$ . This is also the signature of-high temperature stress under unbiased conditions and is attributed to gate sinking.

This letter presents a self-aligned InGaAs quantum-well MOSFET with a transconductance, $g_{m,\max }$ , of 3.45 mS/ $\mu \text{m}$ at $V_{\mathrm {ds}}= 0.5$ V. This is a record value among III-V FETs of any kind, including MOSFETs and HEMTs, and represents an improvement of over 10% with respect to the previous record on planar devices. This result was achieved by redesigning the access regions that link the intrinsic device to the source and drain contacts so as to increase their electron concentration. This mitigates the nonlinear increase of the access resistance at high current. This is often referred to as source starvation and leads to the loss of transconductance under strong on conditions.

Recent advances in the fabrication technology have yielded nanometer-scale InGaAs quantum-well (QW) MOSFETs with extremely low and reproducible external contact and access region resistances. This allows, for the first time, a detailed analysis of the role of ballistic transport in the operation of these devices. This paper presents a systematic analysis of external resistance, ballistic resistance, and channel mobility in InGaAs QW-MOSFETs under near-equilibrium conditions, i.e., under very low drain-source bias. This is an important regime for device characterization. Devices with a wide range of channel lengths, from 70 to 650 nm, are investigated. Our analysis includes the consideration of the impact of carrier degeneracy in the QW channel. We show that unless the ballistic behavior in the intrinsic channel is accounted for, the standard extraction technique for external resistance grossly exaggerates its value as it incorporates the so-called ballistic resistance. By separating out the ballistic resistance, the external resistance in our devices is shown to be extremely low, $74~\Omega $ - $\mu \text{m}$ , including both source and drain sides. This is thanks to our contact-first self-aligned Mo-contact technology. Furthermore, taking the advantage of the wide range of ballisticity of the devices studied in this paper, we demonstrate a methodology to self-consistently extract scattering-dependent effective mobility, mean-free-path length, and ballistic mobility.

© 2013 IEEE. After 50 years of Moore's Law, Si CMOS, the mainstream logic technology, is on a course of diminishing returns. The use of new semiconductor channel materials with improved transport properties over Si offer the potential for device scaling to nanometer dimensions and continued progress. Among new channel materials, III-V compound semiconductors are particularly promising. InGaAs is currently the most attractive candidate for future III-V based n-type MOSFETs while InGaSb is of great interest for p-channel MOSFETs. At the point of most likely deployment, devices based on these semiconductors will have a highly three-dimensional architecture. This paper reviews recent progress toward the development of nanoscale III-V MOSFETs based on InGaAs and InGaSb with emphasis on scalable technologies and device architectures and relevant physics. Progress in recent times has been brisk but much work remains to be done before III-V CMOS can become a reality.

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( $V_{\mathrm{ bs}}$ ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive $V_{\mathrm{ bs}}$ due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate.

It is my great pleasure to announce the winner of the 2019 Electron Devices Society George E. Smith Award given to a letter published in the IEEE Electron Device Letters (EDL) in 2019. The selection was made by vote of EDL’s Editors. The letter is titled “Large-Area 1.2-kV GaN Vertical Power FinFETs With a Record Switching Figure of Merit” and it is authored * by Yuhao Zhang, Min Sun, Josh Perozek, Zhihong Liu, Ahmad Zubair, Daniel Piedra, Nadim Chowdhury, Xiang Gao, Kenneth Shepard, and Tomas Palacios. The letter was published in the January 2019 issue of EDL.

IEEE Electron Device Letters is one of the most selective rapid publication venues within the field of electron devices. This would not be possible without the strong support of the technical professionals—authors and reviewers from academic, industrial, and government institutions worldwide—who have contributed directly to the content and quality of this journal.

Recently, sub-10-nm-diameter InGaAs vertical nanowire (VNW) MOSFETs have been demonstrated. The key to this achievement was the use of Ni for the top ohmic contact. In this paper, we present a detailed study of the impact of Ni and Mo contacts on the electrical characteristics of highly scaled InGaAs VNW MOSFETs. Sequential annealing experiments are presented that reveal the optimum temperature for each type of contact. A negative temperature dependence of the ON-resistance of 7-nm-diameter Ni-contacted devices suggests the existence of an energy barrier. We also observe an unexpected transconductance and drain-induced barrier loweirng (DIBL) dependence on transistor diameter in Ni-contacted devices as well as abnormal DIBL asymmetry to swapping source and drain. All these results can be explained by Ni diffusing down the nanowire during the contact annealing process, reducing the effective channel length, and creating a Schottky-barrier drain.

A novel facile strategy was developed to tune transition-metal oxide electronic states for transistor’s transport enhancement., High electron affinity transition-metal oxides (TMOs) have gained a central role in two-dimensional (2D) electronics by enabling unprecedented surface charge doping efficiency in numerous exotic 2D solid-state semiconductors. Among them, diamond-based 2D electronics are entering a new era by using TMOs as surface acceptors instead of previous molecular-like unstable acceptors. Similarly, surface-doped diamond with TMOs has recently yielded record sheet hole concentrations (2 × 1014 cm−2) and launched the quest for its implementation in microelectronic devices. Regrettably, field-effect transistor operation based on this surface doping has been so far disappointing due to fundamental material obstacles such as (i) carrier scattering induced by nonhomogeneous morphology of TMO surface acceptor layer, (ii) stoichiometry changes caused by typical transistor fabrication process, and (iii) carrier transport loss due to electronic band energy misalignment. This work proposes and demonstrates a general strategy that synergistically surmounts these three barriers by developing an atomic layer deposition of a hydrogenated MoO3 layer as a novel efficient surface charge acceptor for transistors. It shows high surface uniformity, enhanced immunity to harsh fabrication conditions, and benefits from tunable electronic gap states for improving carrier transfer at interfaces. These breakthroughs permit crucial integration of TMO surface doping into transistor fabrication flows and allow outperforming electronic devices to be reached.

We present a detailed study of the off-state leakage current in scaled self-aligned InGaAs FinFETs. In long-channel devices, band-to-band tunneling at the drain-end of the channel is shown to be the root cause of excessive off-state current. This conclusion emerges from its characteristic electric field and temperature behavior and the absence of gate length and fin width dependencies. In short-channel devices, off-state current is significantly larger and it increases as the gate length shortens or the fin widens. We attribute this behavior to current multiplication through the gain of a floating-base parasitic bipolar transistor that is present inside the MOSFET. We extract the bipolar current gain which in short-channel devices is found to increase as the gate length shortens and decrease as the fin width narrows. In long channel devices, the current gain drops exponentially due to base recombination. This has allowed us to extract the diffusion length of electrons in the body of the transistor., DTRA (Grant HDTRA1-14-1-0057), NSF (Grant 0959514)

We demonstrate self-aligned InGaAs FinFETs with fin widths down to 5 nm fabricated through a CMOS compatible front-end process. Precision dry etching of the recess cap results in metal contacts that are about 5 nm away from the intrinsic portion of the fin. The new process has allowed us to fabricate devices with undoped fins and compare them with delta-doped fins. We find that in highly scaled transistors, undoped fin devices show better OFF-state and a tighter VT distribution but similar ON-state characteristics, as compared with δ-doped-fin transistors. 2D Poisson-Schrodinger simulations reveal undoped fins making more effective use of the fin height.

Using a novel gate-last process scheme that affords precise channel thickness control, we have fabricated self-aligned InGaAs quantum-well (QW) MOSFETs. Devices with a channel thickness between 3 and 12 nm, and a gate length between 40 nm and 5 $\mu \text{m}$ are fabricated on a heterostructure that includes a composite InGaAs/InAs QW and an InP barrier. It is observed that channel thickness has a strong impact on the device characteristics. In general, a thick channel is beneficial to ON-state figures of merit, including transconductance and effective carrier mobility. However, a thin channel is beneficial to OFF-state metrics, such as subthreshold swing and drain-induced barrier lowering (DIBL). The InAs composition and effective mass that electrons experience in the channel emerges as a factor that significantly affects channel mobility and presumably the transport characteristics of these devices. The subthreshold swing and DIBL are found to follow a classic scaling behavior. This suggests that the InGaAs QW MOSFETs are at the limit of scaling around $L_{g}=50$ nm.

A number of recent reports have noted excess OFF-state leakage current ( $I_{\mathrm{{\scriptscriptstyle OFF}}})$ in scaled InGaAs quantum-well nMOSFETs. There is growing evidence that a combination of band-to-band tunneling (BTBT) and a floating-body bipolar gain effect is responsible for this. Unless this issue is effectively addressed, the scaling potential of this transistor structure will be compromised. This paper presents a detailed study of the physics of $I_{\mathrm{{\scriptscriptstyle OFF}}}$ and explores $I_{\mathrm{{\scriptscriptstyle OFF}}}$ reduction strategies through 2-D device simulations that have been calibrated with experiments. In essence, under OFF conditions at even moderate values of $V_{\textrm {ds}}$ , a BTBT process at the drain-end generates holes in the channel and thereby reduces the source–channel potential barrier. This results in injection of electrons into the channel that contribute to enhanced $I_{\mathrm{{\scriptscriptstyle OFF}}}$ while the holes are injected into the source where they recombine. In a nanoscale device, the bipolar effect that is at play here can have a very large current gain and amplify many fold even a small BTBT current. A study of approaches to mitigating this effect is analyzed here. It is concluded that the most effective strategy is to minimize the bipolar current gain rather than BTBT in scaled transistors.

We have investigated the role of temperature in the degradation of GaN High-Electron-Mobility-Transistors (HEMTs) under high-power DC stress. We have identified two degradation mechanisms that take place in a sequential manner: the gate leakage current increases first, followed by a decrease in the drain current. Building on this observation, we demonstrate a new scheme to extract the activation energy (Ea) of device degradation from step-temperature measurements on a single device. The Ea’s we obtain closely agree with those extracted from conventional accelerated life test experiments on a similar device technology.

The single-event-transient response of InGaAs MOSFETs exposed to heavy-ion and laser irradiations is investigated. The large barrier between the gate oxide and semiconductor regions effectively suppresses the gate transients compared with other types of III-V FETs. After the initial radiation-induced pulse, electrons and holes flood into the channel region at short time. The electrons are collected efficiently at the drain. The slower moving holes accumulate in the channel and source access region and modulate the source-channel barrier, which provides a pathway for transient source-to-drain current lasting for a few nanoseconds. The peak drain transient current reaches its maximum when the gate bias is near threshold and decreases considerably toward inversion and slightly toward depletion and accumulation. Two-dimensional TCAD simulations are used to understand the charge collection mechanisms.