1. High-Performance Two-Dimensional InSe Field-Effect Transistors with Novel Sandwiched Ohmic Contact for Sub-10 nm Nodes: a Theoretical Study
- Author
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Jiaduo Zhu, Jing Ning, Dong Wang, Jincheng Zhang, Lixin Guo, and Yue Hao
- Subjects
InSe ,Field-effect transistor ,Density functional theory ,Non-equilibrium Green function ,Ohmic contact ,Materials of engineering and construction. Mechanics of materials ,TA401-492 - Abstract
Abstract Two-dimensional (2D) InSe-based field effect transistor (FET) has shown remarkable carrier mobility and high on-off ratio in experimental reports. Theoretical investigations also predicated the high performance can be well preserved at sub-10 nm nodes in the ballistic limit. However, both experimental experience and theoretical calculations pointed out achieving high-quality ohmic has become the main limiting factor for high-performance 2D FET. In this work, we proposed a new sandwiched ohmic contact with indium for InSe FET and comprehensively evaluated its performance from views of material and device based on ab initio methods. The material properties denote that all of fundamental issues of ohmic contact including tunneling barrier, the Schottky barrier, and effective doping are well concerned by introducing the sandwiched structure, and excellent contact resistance was achieved. At device performance level, devices with gate length of 7, 5, and 3 nm were investigated. All metrics of sandwiched contacted devices far exceed requirement of the International Technology Roadmap for Semiconductors (ITRS) and exhibit obvious promotion as compared to conventional structures. Maximum boost of current with 69.4%, 50%, and 49% are achieved for devices with 7, 5, and 3 nm gate length, respectively. Meanwhile, maximum reduction of the intrinsic delay with 20.4%, 16.7%, and 18.9% are attained. Moreover, a benchmark of energy-delay product (EDP) against other 2D FETs is presented. All InSe FETs with sandwiched ohmic contact surpass MoS2 FETs as well as requirement from ITRS 2024. The best result approaches the upper limit of ideal BP FET, denoting superior preponderance of sandwiched structures for InSe FETs in the next generation of complementary metal-oxide semiconductor (CMOS) technology.
- Published
- 2019
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