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The back-gate forward bias method suitable for present standard bulk CMOS processes has been promoted for low-voltage digital circuit application. A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the dc voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed. Guidelines for ensuring proper implementation of the method in a bulk CMOS process have been set up against latch-up, parasitic bipolar, impact ionization, and stand by current. Following these guidelines, a cost-effective low power, low-voltage, high-density mixed mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time.

A three-terminal p - n - p gated lateral bipolar transistor in a counter-type channel p -MOSFET structure has exhibited experimentally ideal I – V characteristics in low-level injection, with a peak current gain exceeding 1000. Two-dimensional device simulation and additional experiments have revealed that high current gains with ideal bipolar I – V characteristics can be obtained only if the counter-type channel is fully depleted. Under this condition, not only the surface emitter-base junction barrier beneath the gate is lowered, but also the holes injected from the emitter almost go through the potential valley in the channel. An analytical model and its validity range have both been established to provide understanding of such behavior, and have been supported experimentally by two-dimensional device simulation. The measured I – V characteristics, including high-level injection, have also been appropriately reproduced.

This paper reports a 1.3 M-pixel CMOS image sensor with 5 /spl mu/m/spl times/5 /spl mu/m pixel size fabricated with a standard 0.35 /spl mu/m CMOS logic process. Three techniques have been applied to improve the chip performance: an N-well photodiode to increase the quantum efficiency for light of long wavelengths; two-stage integration to enhance the performance under high illumination conditions; and capacitor-coupled readout to suppress the column Fixed Pattern Noise (FPN). Random access in rows and downsampling in columns are applicable to both B/W and color sensors.