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This article presents Scaling-computing-in-memory (CIM), an energy-efficient embedded dynamic random access memory (eDRAM)-based in-memory-computing (IMC) accelerator with a dynamic-scaling readout for signal-to-quantization-noise ratio (SQNR) boosting and analog-to-digital converter (ADC) overhead reduction. It greatly saves the ADC cost by reducing the required number of ADC-bit and ADC operations by codesigning the algorithm and hardware. Scaling-CIM proposes three key features: 1) dynamic scaling ADC (DSA) boosts SQNR of multibit operation even with low-bit ADC; 2) adaptive analog bit-parallel (AABP) accumulation reduces the redundant ADC operation; and 3) layer-wise adaptive bit-truncation (LABT) search further enhances efficiency on benchmarks. The Scaling-CIM is fabricated in 28-nm CMOS technology and occupies a 2.03-mm2 die area with an 800-kb eDRAM cell. It achieves 39.7-TOPS/W (8–9 b) energy efficiency on the RestNet-18 benchmark and $1.96\times $ higher efficiency figure of merit (FoM) than the previous IMC-based accelerator.

Human pose estimation (HPE) is a promising solution for accurately understanding the state and context of human actions in virtual reality (VR). A high frame rate with low-power HPE processing is required for a realistic user interaction experience in battery-limited mobile devices. The proposed HPE accelerator is a computing-in-memory (CIM) based accelerator that computes depth-wise separable convolution (DWSC) of a lightweight HPE network. Three key features contribute to a resource-efficient CIM accelerator: 1) Dual-mode CIM computes DWSC with a reconfigurable homogenous architecture, resulting in 2.68 times higher throughput than previous analog CIMs. 2) Effective layer-aware unrolling performs bit-parallel computation on dual-mode CIM with fewer ADC operations, achieving 46 times higher throughput than before. 3) Adaptive fused inter-macro balancing improves latency balance in layer fusion execution, leading to a 57.0% higher frame rate than before. The proposed HPE accelerator is implemented in 28nm CMOS technology. It achieves higher computation resource utilization and operates HPE with a low energy-delay product of 27.6 uJ $\cdot \text{s}$ in mobile VR devices.

This article presents DynaPlasia, a reconfigurable eDRAM-based in- memory computing (IMC) processor with a novel triple-mode cell. It enables higher system-level performance and efficiency in a resource-limited environment. DynaPlasia proposes five key features that can enhance the energy efficiency and area efficiency of the IMC accelerator: 1) dynamic reconfigurable core architecture (DRECA), which dynamically reconfigures the effective IMC macro size according to DNN workloads; 2) the triple-mode cell is reconfigured as IMC PE, unit DAC, and unit cell to optimize system resource utilization adaptively; 3) hierarchical in- memory ADC (Hi-ADC) reduces ADC area overhead with tripe-mode cell and saves power with the hierarchical operation; 4) signed-input signed-weight (SISW) IMC reduces logic switching activity with signed magnitude representation; and 5) leakage-tolerant computing (LTC) to enable high-density cell design. The DynaPlasia is fabricated in 28-nm CMOS technology and occupies a 20.25-mm 2 die area with 9.6-Mb cell capacity. Its measured system peak throughput is 19.5 TOPS (4 b–5 b), and system peak efficiency is 56.0 TOPS/W (4 b–5 b). Even with the ResNet50 @ ImageNet dataset, system efficiency is 29.5 TOPS/W which is 2.5 $\times $ higher than the previous state-of-the-art.