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The use of copper wire in IC packaging has been growing steadily driven by cost effectiveness. However, there are concerns and issues that prevent or delay copper wire bonding technology qualification. Copper wire inherent hardness properties induces higher stress on bond pad and underlying pad structure, which results to inevitable pad crack or damage if pad structure is not robustly design or thin aluminum pad thickness of ≤0.8um for copper wire bonding. Silver alloy wire on the other hand showed great potential in IC packaging around ~20% softer compared to harder copper wire. Copper and silver wire are also cost competitive than gold wire. Both wires may potentially take over gold wire bond especially in handheld devices in the coming years. Compared to gold, silver alloy wire is superior in terms of electrical and thermal conductivity and their mechanical properties are quite similar. Silver and copper wire has similar thermal conductivity and both wires still require inert gas environment like pure nitrogen (N 2 ) and forming gas (95% N 2 , 5%H 2 ) during free-air-ball (FAB) formation. An axisymmetric transient nonlinear dynamic model for fine pitch copper wire bonding was developed with FEM simulation software ABAQUS/Explicit in order to assist in understanding the copper and silver wire bond process focusing on stress or strain investigation at aluminum and low k layers. FEM was focused on Cu wire due to its inherent hardness properties compared to softer silver alloy wire. Simulation result showed that majority of ball bond and Al pad deformation is completed in the very beginning when bond force is applied. Similar to the highest stress on low-k layer is also in the very beginning of bond force application and near the bond pad center area. This study aimed to share the learning, challenges and success story for Cu and silver alloy wire bond characterization using different fine wire diameter sizes for 28nm ultra low-k wafer technology on a FBGA 9×9mm package. Fine wire diameter sizes of 18um, 15um and 13um for both palladium coated Cu (PdCu) and silver (Ag) alloy wire types where characterized and compared based on the output responses results gathered during DOE assessment. Over all wire bond DOE results showed good interaction result with no pad crack/damage for optimum wire bond recipe and validated by FIB cut showing no abnormality on low-k layer. Stress test reliability performances for both wire types were assessed and showed no abnormality. Sliver alloy wire sample wet acid decapsulation process has been a concern once failure analysis is required to ascertain bonding wire connection integrity due to wire corrosion, cracking, thinning and wire easily breaks. With the adoption of laser decapsulation process similar to laser type used in laser grooving of wafer and without using any acid have shown a very good result as depicted in figure 12. A more consistent intermetallic assessment for Ag/Al IMC at ball bond side and easier to quantify similar to conventional Au/Al IMC is recommended as compared to bond pad side having lower Al/Ag IMC with wider variance. Finally, with the combined simulation analysis data, experimental DOE's and initial reliability data result, FBGA 9×9mm package was assembled using a more challenging harder wire type of palladium coated Cu with 18um (0.7mil) wire size. Package reliability qualification per industry JEDEC standard for laminate packages passed with no failure as summarized in table 11.

In this paper, the fundamental understanding of copper (Cu) wire bonding process, and its interaction with the die bond pad surface and structure will be examined, using both Finite Element Analysis (FEA) and experimental study. In the FEA, the Cu wire bonding process is modeled based on dynamic analysis using commercial available finite element software, to investigate the capillary geometry and the bond pad structure designs. In the experimental study, four different factors are evaluated; 1) the inner chamfer angle (ICA) of the capillary, which can affects the ball bond shape formation; 2) the Al pad thickness, and 3) die bond pad coating, which can affects the Al squashing; lastly, 4) the die bond pad structure.

High performance, multi functional and package miniaturization will be the main driving forces that propel the future trend and development of fully integrated multi silicon dies stack using through silicon via (TSV) packaging technology. This paper serves as an extension of the foregoing paper, where TSV-micro C4 solder interconnect were used and stack up to 4-die compared to the 2-die stack previously demonstrated at ECTC 2010[3]. This study is driven by future requirement for memory dies stacking or multiple devices stacking on a thru silicon interposer (TSI). A TSI enables interconnect pitch matching between a high I/Os top chip and a low cost organic substrate however, extension to 4 die stack reveals many daunting assembly challenges for all backend assembly processes. This paper demonstrates with assistance from finite element analysis, actual process verification and reliability test, the required fundamental changes to material properties, bill of material (BOM) and assembly process manufacturability modification in order to achieve feasible assembly process and reliable performance for 4 thin die stacking to an organic substrate using a 1× solder re-flow process and standard flip chip machine in a mass production scenario. This achievement will further strengthen low cost high volume production capability for thru silicon stacking (TSS).

As the progression of 45/40nm ELK devices into mainstream semiconductor assembly manufacturing process increases, the drive to achieve adoption without major changes to process and equipment infrastructure while meeting the superior yield necessary is high. The main goal of this article is to share learning's and provide solutions for integration of 45/40nm ELK devices into Flip Chip and Wire Bond interconnect technology. The scope of this paper covers from FBGA/PBGA for the WB packages and fcCSP for the Flip Chip Devices. The main challenge and focus point for wire bond 45/40nm interconnects is on the 1st bond process. This paper will share some detailed analysis on the following: ✓ WB characterization for 45/40nm ELK ultra-fine-pitch ✓ Key factors for good ball bond integrity and comparison of Au and Cu wire bond process ✓ Recommendations for achieving the required levels of reliability for 45nm Cu ELK integration. The challenges however, for Flip Chip technology are significantly different from the WB process. More and more adoption is being made from conventional eutectic solder bumps or high-lead solder bumps towards the lead-free solder bumps mainly due to the green initiatives. This paper will share analysis on the following: ✓ Thermo-Mechanical Simulation on key input factors and its correlation to actual evaluation results. ✓ Integration of Pb Free ELK Bump with 40nm ELK technology with focus on the critical reflow process. ✓ MUF Technology for Pb Free + ELK devices