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4. Design and implementation of the ‘Tiny RISC’ microprocessor

Author

Jeffrey Gray, Christopher Christensen, A. Abnous, John Lenell, Andrew Naylor, and Nader Bagherzadeh

Subjects
Very-large-scale integration, SIMPLE (military communications protocol), Computer Networks and Communications, business.industry, Computer science, Pipeline (computing), law.invention, Microprocessor, CMOS, Artificial Intelligence, Hardware and Architecture, law, Very long instruction word, Embedded system, business, Software, Computer hardware
Abstract

This paper describes the design and implementation of ‘Tiny RISC’, a 16-bit RISC-style microprocessor designed at UC Irvine. It was fabricated by MOSIS in a 2 μm n-well CMOS technology. Tiny RISC has been designed for optimized data path operation. A simple 32-bit extension of the data path results in a generic functional unit of a VLIW (very long instruction word) processor that is currently being developed at UC Irvine.

Published
1992
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