48 results on '"Jooheung Lee"'
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2. Energy efficient processing of motion estimation for embedded multimedia systems.
3. Write-Amount-Aware Management Policies for STT-RAM Caches.
4. Medical Development Platform Using ZyCAP-Based Partial Reconfiguration on ZynqSoC.
5. Zynq-Based Reconfigurable System for Real-Time Edge Detection of Noisy Video Sequences.
6. Activity-Based Resource Allocation for Motion Estimation Engines.
7. Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors.
8. A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration.
9. A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial Reconfiguration.
10. A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching.
11. Self-Adapting Resource Escalation for Resilient Signal Processing Architectures.
12. Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration.
13. A Fast FPGA Implementation of Tate Pairing in Cryptography over Binary Field.
14. High Performance Array Processor for Video Decoding.
15. An Architecture for Motion Estimation in the Transform Domain.
16. Efficient VLSI implementation of inverse discrete cosine transform [image coding applications].
17. Fault Demotion Using Reconfigurable Slack (FaDReS).
18. Error surface-aware modeling algorithm for quarter-pixel motion estimation.
19. A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration.
20. Reconfigurable Architecture for ZQDCT Using Computational Complexity Prediction and Bitstream Relocation.
21. Efficient VLSI architecture for video transcoding.
22. Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration.
23. Smart Water Pipeline Monitoring System using Wireless Sensor Network
24. Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties.
25. An efficient architecture for motion estimation and compensation in the transform domain.
26. Block-based frequency scalable technique for efficient hierarchical coding.
27. Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study.
28. Write-Amount-Aware Management Policies for STT-RAM Caches
29. Edge Detection System for Noisy Video Sequences Using Partial Reconfiguration
30. Medical Development Platform Using ZyCAP-Based Partial Reconfiguration on ZynqSoC
31. Medical Image Enhancement Algorithm Using Edge-Based Denoising and Adaptive Histogram Stretching
32. Software-Pipelined Academy, Research Institute, and Agency on a 64-Bit Superscalar Processor for High Performance
33. Self-Adapting Resource Escalation for Resilient Signal Processing Architectures
34. Zynq-Based Reconfigurable System for Real-Time Edge Detection of Noisy Video Sequences
35. Improving Energy Efficiency of Block-Matching Motion Estimation Using Dynamic Partial Reconfiguration
36. Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration
37. Efficient VLSI architecture for video transcoding
38. A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration
39. An array-based scalable architecture for DCT computations in video coding
40. Activity-Based Resource Allocation for Motion Estimation Engines
41. Self-reconfigurable approach for computation-intensive motion estimation algorithm in H.264/AVC
42. Activity-Based Resource Allocation for Motion Estimation Engines.
43. A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration.
44. Self-reconfigurable approach for computation-intensive motion estimation algorithm in H.264/AVC.
45. Fault-mitigation by adaptive dynamic reconfiguration for survivable signal-processing architectures
46. Scalable FPGA architecture for DCT computation using dynamic partial reconfiguration
47. Study for Treatment With Calcipotriol/Betamethasone Dipropionate Gel in Korean Patients With Psoriasis Vulgaris (TRIANGLE)
48. Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA
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