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Thin film transistors have become crucial components of several electronic display devices. However, high leakage current is a frustrating impediment to increasing the efficiency of these transistors. We have performed an experimental and quantitative study on the effects of off-state bias stress on the characteristics of a p-type polycrystalline silicon (poly-Si) thin film transistor (TFT). The gate-induced drain leakage (GIDL) current under off-state bias stress conditions was investigated by changing gate-source voltage (Vgs) and drain-source voltage (Vds). Off-state bias stress was found to dramatically increase the threshold Vgs from 1 to 11 V, thereby increasing the voltage needed to turn off the TFT, without causing significant changes in on-state current or subthreshold swing. We developed local defect creation and charge trapping models for a technology computer-aided design simulation platform to understand the mechanisms underlying these observed effects. Using the model, we showed that off-state stress induces charge trapping within the local defects of a high electric field region in the TFT channel near the drain. This reduces the electric field and thermionic field-emission current, which in turn lowers the GIDL current by increasing threshold voltage Vgs.

We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium&ndash, tin&ndash, zinc&ndash, oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH4:N2O, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal&ndash, insulator&ndash, silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH4:N2O = 30:5), the MIS capacitor exhibited the widest memory window, the flat band voltage (&Delta, VFB) shifts of 4.45 V was obtained at the sweep voltage of &plusmn, 11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiOX charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm2/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 &times, 107 were obtained at the initial sweep of the devices. As an NVM, &Delta, VFB was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 &mu, s. The &Delta, VFB was returned to the pristine condition with a negative voltage pulse of &minus, 1 V and 1 &mu, s under a 400&ndash, 700 nm light illumination of ~10 mWcm&minus, 2 in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial &Delta, VFB (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels.

We report the effects of surface passivation by depositing a hydrogenated amorphous silicon (a-Si:H) layer on the electrical characteristics of low temperature polycrystalline silicon thin film transistors (LTPS TFTs). The intrinsic a-Si:H layer was optimized by hydrogen dilution and its structural and electrical characteristics were investigated. The a-Si:H layer in the transition region between a-Si:H and &micro, c-Si:H resulted in superior device characteristics. Using a-Si:H passivation layer, the field-effect mobility of the LTPS TFT was increased by 78.4% compared with conventional LTPS TFT. Moreover, the leakage current measured at VGS of 5 V was suppressed because the defect sites at the poly-Si grain boundaries were well passivated. Our passivation layer, which allows thorough control of the crystallinity and passivation-quality, should be considered as a candidate for high performance LTPS TFTs.

We fabricate amorphous indium–tin–zinc oxide (ITZO) thin film transistors (TFTs), in which the source/drain (S/D) electrodes are composed of metallic Al and nickel Ni. We experimentally investigate the contact characteristics of Al and Ni S/D electrodes using the transmission line method. The ITZO with Al exhibits low field-effect mobility (≤4.8 cm2/Vs) and behaves like a conductor at short channel lengths. Even with a short channel length, the ITZO with Ni exhibits typical field-effect TFT behavior and high field-effect mobility (≥8.1 cm2/Vs), required for a high-resolution display. We present a mechanism to dope oxygen vacancies in the S/D regions to account for the differences in the properties of the ITZO TFTs with Al and Ni electrodes. Using a technology computer-aided design (TCAD) simulation, we show that the oxygen vacancies ( V O + ) could diffuse from the Al and Ni S/D electrodes at a substrate temperature of 350 °C in 30 min, and find that their diffusion coefficient and activation energy are 2.8 × 10−8 cm2/s and 0.45 eV, respectively. Further, the S/D doping concentrations of V O + are 3.47 × 1019 and 1.55 × 1017/cm3 at the Al and Ni interfaces, respectively. The lateral diffusion profiles of V O + are different for the Al and Ni electrodes, which caused a difference in the drain current to gate voltage transfer characteristics of each electrode.