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Spin transfer torque magnetic random access memory (STT-MRAM) has recently been a compelling candidate for next-generation memory. However, with the gradual scaling down of technology, the read reliability issue is emerging as a new challenge for STT-MRAM due to the increasing process variation and decreasing supply voltage. In addition, due to high read disturbance, it is difficult to increase read cell current to increase the sense margin. This paper proposes an offset-canceling sensing scheme using two capacitors, to improve sensing margin and accelerate read speed. Simulations using 28nm processes are run to demonstrate the performance of the proposed sensing circuit. According to the simulation results, the read error rate of the proposed sense scheme reaches 5.79E-06 with the read time of 1.8nsec.

Running a convolutional neural network (CNN) algorithm using dedicated integrated circuits (ICs) on real-time portable applications is mainly restricted by slow performance and large power consumption. The power and delay are mainly due to external memory access, which incurs considerable energy consumption and bandwidth issues. In this paper, we propose an efficient convolution layer design using domain wall memory (DWM) for eliminating external memory access in image sensor embedded applications. A low energy access scheme using tag is employed to further reduce power consumption. The experimental results show that the proposed CNN architecture achieves 11.2% memory energy savings and 21.8% of MAC operation reduction compared to conventional architecture.

Due to the leakage power of CMOS-based memory, Nonvolatile magnetic memory is considered a strong candidate to replace the CMOS-based memory. Spin transfer torque magnetic random access memory (STT-MRAM) is one of the most promising candidates, but it still has many shortcomings related to the write operation. Compared to STT-MRAM, spin orbit torque magnetic random access memory (SOT-MRAM) is the next generation of nonvolatile magnetic memory because of its relatively good performance and low power. Although SOT-MRAM has various advantages over STT-MRAM, a significant reduction in write power is required to meet the power level of CMOS-based memory. In this paper, we present a low power SOT-MRAM cell configuration using the dual write operation. By writing on two cells simultaneously, write energy can be reduced depending on data patterns. Compared to the conventional 2T-1MTJ SOT-MRAM, the proposed SOT-MRAM cell with the dual write scheme reduces the write energy by 26.3% on average.